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US-20260129881-A1 - THIN FILM RESISTOR AND THIN FILM METAL-INSULATOR-METAL CAPACITOR IN INTEGRATED CIRCUIT

US20260129881A1US 20260129881 A1US20260129881 A1US 20260129881A1US-20260129881-A1

Abstract

A method is provided for forming a thin film resistor (TFR) and a thin film MIM capacitor (TFMIMCAP) in an integrated circuit (IC) device. A method comprises: forming a thin film layer over an integrated circuit (IC) structure; annealing the thin film layer; and forming first and second thin film elements in the thin film layer. An integrated circuit device comprises: an integrated circuit (IC) structure; an annealed thin film layer above the IC structure; and first and second thin film elements in the thin film layer.

Inventors

  • Paul Fest
  • Brandon Lent
  • Jeff Peters
  • Kevin Clark

Assignees

  • MICROCHIP TECHNOLOGY INCORPORATED

Dates

Publication Date
20260507
Application Date
20250422

Claims (20)

  1. 1 . A method comprising: forming a thin film layer over an integrated circuit (IC) structure; annealing the thin film layer; and forming first and second thin film elements in the thin film layer.
  2. 2 . The method of claim 1 , wherein the first thin film element comprises a thin film resistor (TFR), and wherein the second thin film element comprises a thin film metal-insulator-metal capacitor (TFMIMCAP).
  3. 3 . The method of claim 1 , wherein forming first and second thin film elements comprises: forming a thin film hardmask layer over the thin film layer; forming and patterning a photomask over the thin film hardmask layer; performing a first etch process to remove selected portions of the thin film hardmask layer to define a thin film hardmask, wherein the first etch process stops at the thin film layer; removing the photomask; and performing a second etch process using the thin film hardmask as a hardmask to remove selected portions of the thin film layer to define the first thin film element and the second thin film element under the thin film hardmask.
  4. 4 . The method of claim 3 , wherein the thin film hardmask layer comprises silicon nitride (SiN).
  5. 5 . The method of claim 3 , wherein the second etch process rounds upper corners of the thin film hardmask.
  6. 6 . The method of claim 3 , comprising forming a dielectric etch stop layer over the IC structure prior to forming the thin film layer, wherein the second etch process stops at the dielectric etch stop layer.
  7. 7 . The method of claim 3 , comprising: forming an oxide insulator/capacitance layer; performing a third etch process to form a first oxide layer opening in the oxide layer over the first thin film element and a second oxide layer opening in the oxide insulator/capacitance layer over the second thin film element; performing a fourth etch process through the first and second oxide layer openings to form first and second thin film contact openings in the thin film hardmask over the first and second thin film elements, respectively, thereby exposing surfaces of the first and second thin film elements, respectively; and forming a metal interconnect layer, over the IC structure, comprising: a first metal interconnect element coupled to at least one of the plurality of conductive IC element contacts, a second metal interconnect extending into the first thin film contact opening to contact the underlying first thin film element, and a third metal interconnect extending into the second thin film contact opening to contact the underlying second thin film element.
  8. 8 . The method of claim 7 , wherein the metal interconnect layer comprises aluminum (Al), aluminum silicon (AlSi), or aluminum silicon copper (AlSiCu).
  9. 9 . The method of claim 1 , wherein the IC structure includes a transistor including at least one conductive IC element contact connected to at least one of a source region, a drain region, and a gate region of the transistor.
  10. 10 . The method of claim 1 , wherein the thin film layer comprises silicon carbon chromium (SiCCr), silicon chromium (SiCr), chromium silicon nitride (CrSiN), tantalum nitride (TaN), tantalum silicide (Ta 2 Si), or titanium nitride (TiN).
  11. 11 . The method of claim 1 , wherein annealing comprises heating the thin film layer at a temperature of at least 500° C. for at least 20 minutes.
  12. 12 . The method of claim 7 , comprising annealing the thin film layer at a time after forming the thin film layer and before forming the metal interconnect layer.
  13. 13 . An integrated circuit device comprising: an integrated circuit (IC) structure; an annealed thin film layer above the IC structure; and first and second thin film elements in the thin film layer.
  14. 14 . The integrated circuit device of claim 13 , wherein the first thin film element is a thin film resistor, and wherein the second thin film element is a thin film metal-insulator-metal capacitor.
  15. 15 . The integrated circuit device of claim 14 , comprising a metal interconnect layer, over the IC structure, comprising aluminum (Al), aluminum silicon (AlSi), or aluminum silicon copper (AlSiCu), and comprising: a first metal interconnect element coupled to a conductive IC element contact, a second metal interconnect coupled to the thin film resistor, and a third metal interconnect coupled to the thin film metal-insulator-metal capacitor.
  16. 16 . The integrated circuit device of claim 13 , wherein the IC structure includes a transistor including at least one conductive IC element contact connected to at least one of a source region, a drain region, and a gate region of the transistor.
  17. 17 . The integrated circuit device of claim 13 , wherein the thin film layer comprises silicon carbon chromium (SiCCr), silicon chromium (SiCr), chromium silicon nitride (CrSiN), tantalum nitride (TaN), tantalum silicide (Ta 2 Si), or titanium nitride (TiN).
  18. 18 . An integrated circuit device comprising: an integrated circuit (IC) structure; an annealed thin film layer, above the IC structure, comprising silicon carbon chromium (SiCCr), silicon chromium (SiCr), chromium silicon nitride (CrSiN), tantalum nitride (TaN), tantalum silicide (Ta 2 Si), or titanium nitride (TiN); a thin film hardmask layer, over the thin film layer, comprising silicon nitride (SiN); a thin film resistor in the thin film layer; and a thin film metal-insulator-metal capacitor in the thin film layer.
  19. 19 . The integrated circuit device of claim 18 , comprising a metal interconnect layer, over the IC structure, comprising aluminum (Al), aluminum silicon (AlSi), or aluminum silicon copper (AlSiCu), and comprising: a first metal interconnect element coupled to a conductive IC element contact, a second metal interconnect coupled to the thin film resistor, and a third metal interconnect coupled to the thin film metal-insulator-metal capacitor.
  20. 20 . The integrated circuit device of claim 18 , wherein the IC structure includes a transistor including at least one conductive IC element contact connected to at least one of a source region, a drain region, and a gate region of the transistor.

Description

RELATED PATENT APPLICATION This application claims priority to commonly owned United States Provisional Patent Application No. 63/716,899 filed Nov. 6, 2024, the entire contents of which are hereby incorporated by reference for all purposes. TECHNICAL FIELD The present disclosure relates to thin film resistors (TFRs) and thin film metal-insulator-metal capacitors (TFMIMCAPs) and methods for forming TFRs and TFMIMCAPs, in particular, TFRs and TFMIMCAPs in integrated circuits and methods for forming TFRs and TFMIMCAPs in integrated circuits. BACKGROUND Semiconductor device technologies may integrate many different functions on a single chip. For example, analog and digital circuits may be produced on a single chip. Capacitors and resistors may be components in electrical circuits. A thin film resistor (TFR) may include any suitable resistive film formed on or in an insulating substrate. Some common IC-integrated TFR resistive film materials include SiCr, SiCCr, TaN, and TiN. Thin film resistors (TFR), typically made of deposited homogenous metal thin film, offer technical advantages in terms of low temperature coefficient of resistance, smooth electron flow and long-term stability, which make them suitable for use in high precision radio frequency applications. Fabricating integrated TFRs typically employs the addition of numerous processing steps to the backend IC integration flow, such as several expensive photomask processes. In semiconductor devices, it is desirable for capacitors to be small in size while having large capacitances. A MIM capacitor, such as a thin film metal-insulator-metal (TFMIMCAP) capacitor, may be capable of achieving a large capacitance while being small in size. Additionally, in semiconductor devices, it is desirable for capacitors to have a low voltage coefficient. The voltage coefficient is a measure of how much the capacitor varies with voltage. A MIM capacitor, such as a thin film metal-insulator-metal (TFMIMCAP) capacitor, may be capable of achieving a low voltage coefficient. A MIM capacitor is typically formed within the interconnect layers of an integrated circuit. Semiconductor devices often have both capacitors and resistors integrated into a small area. Many integrated circuit (“IC”) devices incorporate thin film resistors (TFRs) or thin film MIM capacitors via fabrication of a Back-End-Of-Line (BEOL) structure. In conventional semiconductor fabrication processes, the MIM capacitor and the TFR are fabricated separately. The thin film suitable for forming the TFR is typically too resistive to be used as the MIM capacitor plate. Also, the thinness of the TFR usually imposes a particular patterning and etching process to form good electrical contact without damage to the thin resistor material. As such, adding a TFR to an integrated circuit including a MIM capacitor and vice-versa, typically results in significant additional cycle time and cost. There is a need for low-cost methods for integrating thin film resistors (TFRs) and thin film metal-insulator-metal capacitors (TFMIMCAPs) in integrated circuits. SUMMARY OF THE INVENTION According to an aspect, there is provided a method comprising: forming a thin film layer over an integrated circuit (IC) structure; annealing the thin film layer; and forming first and second thin film elements in the thin film layer. An aspect provides a method as in the preceding paragraph, wherein the first thin film element comprises a thin film resistor (TFR), and wherein the second thin film element comprises a thin film metal-insulator-metal capacitor (TFMIMCAP). An aspect provides a method as in one of the preceding two paragraphs, wherein forming first and second thin film elements comprises: forming a thin film hardmask layer over the thin film layer; forming and patterning a photomask over the thin film hardmask layer; performing a first etch process to remove selected portions of the thin film hardmask layer to define a thin film hardmask, wherein the first etch process stops at the thin film layer; removing the photomask; and performing a second etch process using the thin film hardmask as a hardmask to remove selected portions of the thin film layer to define the first thin film element and the second thin film element under the thin film hardmask. An aspect provides a method as in one of the preceding three paragraphs, wherein the thin film hardmask layer comprises silicon nitride (SiN). An aspect provides a method as in one of the preceding four paragraphs, wherein the second etch process rounds upper corners of the thin film hardmask. An aspect provides a method as in one of the preceding five paragraphs, comprising forming a dielectric etch stop layer over the IC structure prior to forming the thin film layer, wherein the second etch process stops at the dielectric etch stop layer. An aspect provides a method as in one of the preceding six paragraphs, comprising: forming an oxide insulator/capacitance layer; performing a third etc