US-20260129885-A1 - INTEGRATED CIRCUIT DEVICES INCLUDING HIGH-DENSITY CAPACITORS

Abstract

An integrated circuit device includes a substrate, and a metal-oxide-semiconductor capacitor (MOSCAP) on the substrate. The MOSCAP includes a lower semiconductor device on the substrate, the lower semiconductor device including a pair of lower source/drain regions and a lower gate structure between the pair of lower source/drain regions, and an upper semiconductor device on the lower semiconductor device, the upper semiconductor device including a pair of upper source/drain regions and an upper gate structure between the pair of upper source/drain regions. The lower gate structure is electrically connected to both of the pair of upper source/drain regions.

Inventors

• Hyo Jong SHIN
• Beomjin PARK
• Jongmin Shin
• Young Gook Park
• Kang-ill Seo

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20250613

Claims (20)

1. 1 . An integrated circuit device, comprising: a substrate; and a metal-oxide-semiconductor capacitor (MOSCAP) on the substrate, the MOSCAP comprising: a lower semiconductor device on the substrate, the lower semiconductor device comprising a pair of lower source/drain regions and a lower gate structure between the pair of lower source/drain regions; and an upper semiconductor device on the lower semiconductor device, the upper semiconductor device comprising a pair of upper source/drain regions and an upper gate structure between the pair of upper source/drain regions, wherein the lower gate structure is electrically connected to both of the pair of upper source/drain regions.
2. 2 . The integrated circuit device of claim 1 , wherein the upper gate structure is electrically connected to both of the pair of lower source/drain regions.
3. 3 . The integrated circuit device of claim 1 , wherein the MOSCAP further comprises an isolation region between the lower gate structure and the upper gate structure, and wherein the lower gate structure is electrically separated from the upper gate structure by the isolation region.
4. 4 . The integrated circuit device of claim 1 , wherein the lower gate structure is configured to receive a first voltage, and wherein the upper gate structure is configured to receive a second voltage different from the first voltage.
5. 5 . The integrated circuit device of claim 1 , wherein the lower semiconductor device further comprises a plurality of lower channel layers between the pair of lower source/drain regions, the lower channel layers spaced apart from each other in a direction perpendicular to an upper surface of the substrate, and wherein the upper semiconductor device further comprises a plurality of upper channel layers between the pair of upper source/drain regions, the upper channel layers spaced apart from each other in the direction.
6. 6 . The integrated circuit device of claim 1 , wherein the pair of lower source/drain regions have a first conductivity type, and wherein the pair of upper source/drain regions have a second conductivity type different from the first conductivity type.
7. 7 . The integrated circuit device of claim 1 , wherein the lower gate structure and the upper gate structure are configured to receive a first voltage and a second voltage, respectively, and wherein the MOSCAP is configured to have a maximum capacitance value when the first and second voltages cause the lower semiconductor device and the upper semiconductor device to both operate in an inversion region.
8. 8 . An integrated circuit device, comprising: a substrate; a frontside metal-oxide-metal capacitor (MOMCAP) on a first surface of the substrate; and a backside MOMCAP on a second surface of the substrate opposite the first surface, the backside MOMCAP electrically connected to the frontside MOMCAP.
9. 9 . The integrated circuit device of claim 8 , wherein the backside MOMCAP comprises an upper backside metallization pattern that includes a plurality of interdigitated upper backside fingers, and wherein the interdigitated upper backside fingers extend in a first direction parallel to the first surface of the substrate and are spaced apart from each other in a second direction intersecting the first direction.
10. 10 . The integrated circuit device of claim 9 , further comprising a semiconductor device on the first surface of the substrate, the semiconductor device comprising a pair of source/drain regions and a gate structure between the pair of source/drain regions, wherein the gate structure extends in the second direction and overlaps at least one of the interdigitated upper backside fingers in a third direction perpendicular to the first surface of the substrate.
11. 11 . The integrated circuit device of claim 9 , wherein the upper backside metallization pattern includes a first upper backside metallization layer that comprises first ones of the interdigitated upper backside fingers, and a second upper backside metallization layer that comprises second ones of the interdigitated upper backside fingers, wherein the first upper backside metallization layer is capacitively coupled to the second upper backside metallization layer, and wherein the backside MOMCAP further comprises an insulating layer between the first upper backside metallization layer and the second upper backside metallization layer.
12. 12 . The integrated circuit device of claim 9 , wherein the backside MOMCAP further comprises a lower backside metallization pattern on a lower surface of the upper backside metallization pattern, the lower backside metallization pattern including a plurality of interdigitated lower backside fingers, and wherein the interdigitated lower backside fingers extend in the second direction and are spaced apart from each other in the first direction.
13. 13 . The integrated circuit device of claim 12 , wherein the backside MOMCAP further comprises a backside insulating layer between the lower backside metallization pattern and the upper backside metallization pattern in a third direction perpendicular to the first surface of the substrate, and wherein at least one of the interdigitated upper backside fingers overlaps at least one of the interdigitated lower backside fingers in the third direction.
14. 14 . The integrated circuit device of claim 8 , further comprising a metal-oxide-semiconductor capacitor (MOSCAP) between the frontside MOMCAP and the backside MOMCAP, wherein the MOSCAP comprises: a lower semiconductor device on the substrate, the lower semiconductor device comprising a pair of lower source/drain regions and a lower gate structure between the pair of lower source/drain regions; and an upper semiconductor device on the lower semiconductor device, the upper semiconductor device comprising a pair of upper source/drain regions and an upper gate structure between the pair of upper source/drain regions.
15. 15 . The integrated circuit device of claim 14 , further comprising an upper source/drain contact structure that extends between the frontside MOMCAP and the backside MOMCAP, wherein a first one of the pair of upper source/drain regions is electrically connected to both the frontside MOMCAP and the backside MOMCAP through the upper source/drain contact structure.
16. 16 . The integrated circuit device of claim 14 , further comprising a lower source/drain contact structure that extends between the frontside MOMCAP and the backside MOMCAP, wherein a first one of the pair of lower source/drain regions is electrically connected to both the frontside MOMCAP and the backside MOMCAP through the lower source/drain contact structure.
17. 17 . An integrated circuit device, comprising: a substrate; a metal-oxide-semiconductor capacitor (MOSCAP) on a first surface of the substrate; and a backside metal-oxide-metal capacitor (MOMCAP) on a second surface of the substrate opposite the first surface, the backside MOMCAP electrically connected to the MOSCAP.
18. 18 . The integrated circuit device of claim 17 , wherein the MOSCAP comprises: a lower semiconductor device on the substrate, the lower semiconductor device comprising a pair of lower source/drain regions and a lower gate structure between the pair of lower source/drain regions; and an upper semiconductor device on the lower semiconductor device, the upper semiconductor device comprising a pair of upper source/drain regions and an upper gate structure between the pair of upper source/drain regions.
19. 19 . The integrated circuit device of claim 18 , further comprising a lower gate contact that extends into the substrate, wherein the lower gate structure is electrically connected to the backside MOMCAP through the lower gate contact.
20. 20 . The integrated circuit device of claim 18 , further comprising a lower source/drain contact structure that extends into the substrate, wherein a first one of the pair of lower source/drain regions is electrically connected to the backside MOMCAP through the lower source/drain contact structure.

Description

RELATED APPLICATIONS The present application claims the benefit of U.S. Provisional Patent Application Ser. No. 63/716,473, filed on Nov. 5, 2024, entitled INTEGRATED CIRCUIT DEVICES AND METHODS OF FORMING THE SAME, the disclosure of which is hereby incorporated herein in its entirety by reference. TECHNICAL FIELD The present disclosure generally relates to the field of integrated circuit devices and, more particularly, to integrated circuit devices including high-density capacitors. BACKGROUND OF THE INVENTION The size of transistors in integrated circuit (IC) devices has continued to decrease to down-scale logic elements. This has resulted in the development of gate-all-around (GAA) structures such as multi-bridge channel field-effect transistors (MBCFETs™) and nanosheet FETs (NSFETs). Moreover, as technology to increase transistor density has continued to develop, three-dimensional (3D) device structures, such as stacked transistors, are under consideration. A stacked transistor (or a “transistor stack”) may include a first transistor and a second transistor. The first transistor may be a first type of transistor (e.g., an n-type metal-oxide-semiconductor (NMOS) transistor) and the second transistor may be a second type of transistor (e.g., a p-type metal-oxide-semiconductor (PMOS) transistor). The first and second types of transistors may be complementary to each other, and thus may be part of a complementary metal-oxide-semiconductor (CMOS) structure. The first and second transistors may be stacked in any order (e.g., first on top of second, or second on top of first), thereby resulting in a stack comprising an upper transistor and a lower transistor. SUMMARY OF THE INVENTION An integrated circuit device, according to some embodiments herein, may include a substrate, and a metal-oxide-semiconductor capacitor (MOSCAP) on the substrate, the MOSCAP comprising a lower semiconductor device on the substrate, the lower semiconductor device comprising a pair of lower source/drain regions and a lower gate structure between the pair of lower source/drain regions, and an upper semiconductor device on the lower semiconductor device, the upper semiconductor device comprising a pair of upper source/drain regions and an upper gate structure between the pair of upper source/drain regions. The lower gate structure may be electrically connected to both of the pair of upper source/drain regions. An integrated circuit device, according to some embodiments herein, may include a substrate, a frontside metal-oxide-metal capacitor (MOMCAP) on a first surface of the substrate, and a backside MOMCAP on a second surface of the substrate opposite the first surface, the backside MOMCAP electrically connected to the frontside MOMCAP. An integrated circuit device, according to some embodiments herein, may include a substrate, a metal-oxide-semiconductor capacitor (MOSCAP) on a first surface of the substrate, and a backside metal-oxide-metal capacitor (MOMCAP) on a second surface of the substrate opposite the first surface, the backside MOMCAP electrically connected to the MOSCAP. Example embodiments of the present application result, in part, from the realization that it may be advantageous to provide one or more high-density capacitors in an integrated circuit device by modifying the existing architecture used to form three-dimensional (3D) stacked transistors, such as 3D stacked field-effect transistors (3DSFETs), in the integrated circuit device, to thereby simplify a fabrication process for the high-density capacitors and reduce fabrication costs associated therewith. For example, the high-density capacitors may function as decoupling capacitors that help provide a stable voltage supply and/or filter out noise within the integrated circuit device. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a conventional integrated circuit device. FIG. 2A is a schematic block diagram of a transistor stack of an integrated circuit device according to some embodiments. FIG. 2B is a schematic plan view of an integrated circuit device according to some embodiments. FIG. 2C is a schematic cross-sectional view taken along line A-A′ of FIG. 2B. FIG. 2D is a schematic cross-sectional view taken along line B-B′ of FIG. 2B. FIG. 3A is a schematic block diagram of a MOSCAP of an integrated circuit device according to some embodiments. FIG. 3B is a schematic plan view of an integrated circuit device according to some embodiments. FIG. 3C is a schematic cross-sectional view taken along line B-B′ of FIG. 3B. FIG. 3D is a schematic cross-sectional view taken along line C-C′ of FIG. 3B. FIG. 3E is a schematic cross-sectional view taken along line D-D′ of FIG. 3B. FIG. 3F is a schematic plan view of a frontside MOMCAP according to some embodiments. FIG. 3G is a schematic plan view of an integrated circuit device including the frontside MOMCAP of FIG. 3F according to some embodiments. FIG. 3H is a schematic plan view of a back