US-20260129886-A1 - SEMICONDUCTOR DEVICE

Abstract

A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate, at least one support layer in contact with the plurality of lower electrodes and extending in a direction, parallel to an upper surface of the substrate, an upper electrode disposed on the plurality of lower electrodes and the at least one support layer, a dielectric layer between the plurality of lower electrodes and the upper electrode and between the at least one support layer and the upper electrode, and a blocking layer disposed between the at least one support layer and the dielectric layer, and including a material having a bandgap energy greater than a bandgap energy of a material of the at least one support layer. The dielectric layer is in contact with the plurality of lower electrodes and is spaced apart from the at least one support layer by the blocking layer.

Inventors

• Intak Jeon
• HanJin LIM
• HyungSuk Jung

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20251220

Priority Date

20220526

Claims (20)

1. 1 . A method of manufacturing a semiconductor device, the method comprising: forming lower electrodes on a substrate; forming at least one support layer supporting the lower electrodes; forming a blocking layer on the at least one support layer; forming a dielectric layer on the lower electrodes and the blocking layer; and forming an upper electrode on the dielectric layer, wherein the blocking layer has a thickness less than a thickness of the dielectric layer.
2. 2 . The method as claimed in claim 1 , wherein forming the blocking layer includes performing an Area Selective Atomic Layer Deposition process, and wherein the blocking layer is selectively formed on the at least one support layer and is not formed on the lower electrodes.
3. 3 . The method as claimed in claim 2 , wherein the Area Selective Atomic Layer Deposition process includes supplying a precursor including a metal compound, supplying a reactive gas and supplying an inhibitor capable of inhibiting deposition on surfaces of the lower electrodes, and wherein the reactive gas includes H 2 O, H 2 O 2 O 2 O 3 H 2 NH 3 N 2 or the like.
4. 4 . The method as claimed in claim 1 , wherein the blocking layer is formed of aluminum oxide, zirconium oxide, lanthanum oxide, hafnium oxide, yttrium oxide, beryllium oxide, magnesium oxide, silicon oxide, hafnium silicon oxide, zirconium silicon oxide, or combinations thereof.
5. 5 . The method as claimed in claim 1 , wherein the blocking layer is formed of a material having a bandgap energy greater than a bandgap energy of the at least one support layer.
6. 6 . The method as claimed in claim 1 , wherein the blocking layer includes at least one portion of which a thickness changes as the blocking layer approaches side surfaces of the lower electrodes.
7. 7 . The method as claimed in claim 1 , wherein the blocking layer extends along a surface of the at least one support layer.
8. 8 . The method as claimed in claim 1 , wherein the at least one support layer includes silicon nitride, silicon oxynitride, silicon carbonitride, or silicon boron nitride.
9. 9 . The method as claimed in claim 1 , wherein the blocking layer includes a material having a bandgap energy of about 5.0 eV or greater.
10. 10 . The method as claimed in claim 1 , wherein the blocking layer includes a material having a bandgap energy of about 7.0 eV or greater.
11. 11 . The method as claimed in claim 1 , wherein each of the lower electrodes includes a conductive layer and an interfacial film between the conductive layer and the dielectric layer, and wherein the interfacial film extends vertically along a side surface of the conductive layer from a region adjacent to an edge of the blocking layer.
12. 12 . A method of manufacturing a semiconductor device, the method comprising: forming an etch stop layer; forming lower electrodes on a substrate penetrating the etch stop layer; forming at least one support layer supporting the lower electrodes; forming a first blocking layer on a surface of the at least one support layer; forming a second blocking layer on the etch stop layer; forming a dielectric layer on the lower electrodes, the first blocking layer, and the second blocking layer; and forming an upper electrode on the dielectric layer, wherein the first blocking layer has a thickness less than a thickness of the dielectric layer.
13. 13 . The method as claimed in claim 12 , wherein the second blocking layer is not formed on surfaces of the lower electrodes.
14. 14 . The method as claimed in claim 12 , wherein the second blocking layer is formed of a material having a bandgap energy greater than a bandgap energy of the at least one support layer.
15. 15 . The method as claimed in claim 12 , wherein the second blocking layer is formed together in the same process as the first blocking layer.
16. 16 . The method as claimed in claim 12 , wherein the second blocking layer has a thickness less than the thickness of the dielectric layer.
17. 17 . The method as claimed in claim 12 , wherein the second blocking layer includes at least one portion of which a thickness changes as the second blocking layer approaches side surfaces of the lower electrodes.
18. 18 . A method of manufacturing a semiconductor device, the method comprising: forming a lower structure including a substrate and upper conductive patterns on the substrate; forming an etch stop layer; forming mold layers and at least one first support layer on the etch stop layer; forming a plurality of holes passing through the mold layers and the at least one first support layer to expose the upper conductive patterns; forming lower electrodes in the plurality of holes and on the upper conductive patterns; forming at least one second support layer by removing at least a portion of the at least one first support layer, the at least one second support layer supporting the lower electrodes; forming a blocking layer on the at least one second support layer; forming a dielectric layer on the lower electrodes and the blocking layer; and forming an upper electrode on the dielectric layer, wherein the blocking layer has a thickness less than a thickness of the dielectric layer.
19. 19 . The method as claimed in claim 18 , wherein the lower structure further comprising: an active region on the substrate; a word line intersecting the active region; a bit line on the word line; and a contact structure on a side surface of the bit line and electrically connecting a portion of the active region to one of the lower electrodes, and wherein the contact structure includes the upper conductive patterns.
20. 20 . The method as claimed in claim 18 , further comprising removing the mold layers before forming the blocking layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is continuation of U.S. Application No. 18/095,561, filed on January 11, 2023, in the U.S. Patent and Trademark Office, which claims priority and the benefit thereof under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0064505, filed on May 26, 2022, in the Korean Intellectual Property Office, the entire disclosures of al of which are incorporated herein by reference for all purposes. BACKGROUND 1. Field Embodiments relate to a semiconductor device. 2. Description of the Related Art In accordance with a demand for high integration and miniaturization of semiconductor devices, the size of the capacitor of the semiconductor device is also miniaturized. Accordingly, research into optimizing the structure of a capacitor capable of storing information in a dynamic random-access memory (DRAM) has been variously attempted. SUMMARY According to an example embodiment, a semiconductor device includes a substrate; a plurality of lower electrodes disposed on the substrate; at least one support layer in contact with the plurality of lower electrodes and extending in a direction, parallel to an upper surface of the substrate; an upper electrode disposed on the plurality of lower electrodes and the at least one support layer; a dielectric layer between the plurality of lower electrodes and the upper electrode and between the at least one support layer and the upper electrode; and a blocking layer disposed between the at least one support layer and the dielectric layer, and including a material having a bandgap energy greater than a bandgap energy of a material of the at least one support layer. The dielectric layer is in contact with the plurality of lower electrodes and is spaced apart from the at least one support layer by the blocking layer. According to an example embodiment, a semiconductor device includes a plurality of contact structures on a substrate; an etch stop layer on the plurality of contact structures; a plurality of lower electrodes passing through the etch stop layer, and connected to the plurality of contact structures respectively; at least one support layer in contact with the plurality of lower electrodes and extending in a direction, parallel to an upper surface of the substrate; an upper electrode disposed on the plurality of lower electrodes and the at least one support layer; a dielectric layer between the plurality of lower electrodes and the upper electrode and between the at least one support layer and the upper electrode; a first blocking layer disposed between the at least one support layer and the dielectric layer, and including a material having a bandgap energy greater than a bandgap energy of a material of the at least one support layer; and a second blocking layer disposed between the etch stop layer and the dielectric layer, and including a material having a bandgap energy greater than a bandgap energy of a material of the at least one support layer. According to an example embodiment, a semiconductor device includes a substrate; a plurality of lower electrodes disposed on the substrate, each of the plurality of lower electrodes including a conductive layer and an interfacial film extending along at least one surface of the conductive layer; at least one support layer in contact with a portion of a side surface of the conductive layer and extending in a direction, parallel to an upper surface of the substrate; an upper electrode disposed on the plurality of lower electrodes and the at least one support layer; a dielectric layer in contact with the interfacial film, and disposed between the interfacial film and the upper electrode and between the at least one support layer and the upper electrode; and a blocking layer disposed between the at least one support layer and the dielectric layer and in contact with the at least one support layer and the dielectric layer, the blocking layer including a material having a bandgap energy greater than a bandgap energy of a material of the at least one support layer. According to an example embodiment, a method of manufacturing a semiconductor device includes forming lower electrodes and at least one support layer supporting the lower electrodes, on a substrate; forming a first blocking layer on a surface of the at least one support layer, using an Area Selective Atomic Layer Deposition process; forming a dielectric layer on the lower electrodes and the first blocking layer; and forming an upper electrode disposed on the dielectric layer. BRIEF DESCRIPTION OF DRAWINGS Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which: FIG. 1 is a schematic plan view of a semiconductor device according to example embodiments; FIG. 2 is a schematic cross-sectional view of a semiconductor device according to example embodiments; FIG. 3 is a partially enlarged cross-sectional view of area ‘A’ includin