US-20260129887-A1 - SEMICONDUCTOR STRUCTURE HAVING CAPACITOR AND METHOD OF MANUFACTURING THEREOF

US20260129887A1US 20260129887 A1US20260129887 A1US 20260129887A1US-20260129887-A1

Abstract

A semiconductor structure includes a substrate having a surface, and a capacitor structure disposed within the substrate and having a bottom portion, a sidewall portion disposed over and coupled to the bottom portion, and an upper portion coupled to the sidewall portion and exposed through the surface. The semiconductor structure further includes a semiconductor device disposed over and separated from the capacitor structure. The sidewall portion is disposed between the bottom portion and the upper portion, and at least a portion of the semiconductor device is surrounded by the sidewall portion of the capacitor structure from a plan view.

Inventors

Hung-Te Lin

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Dates

Publication Date: 20260507
Application Date: 20241106

Claims (20)

1 . A semiconductor structure, comprising: a substrate; a capacitor structure disposed within the substrate and having a bottom portion and a sidewall portion disposed over and coupled to the bottom portion; a first isolation layer disposed over the capacitor structure and within the substrate; and a semiconductor device disposed over the first isolation layer and including an oxide layer disposed over a first surface of the substrate; wherein the first isolation layer is enclosed by the oxide layer and the capacitor structure, at least a portion of the semiconductor device is surrounded by the sidewall portion of the capacitor structure, and the semiconductor device is separated from the capacitor structure.
2 . The semiconductor structure of claim 1 , wherein the capacitor structure further includes an upper portion coupled to the sidewall portion, the sidewall portion is disposed between the bottom portion and the upper portion, and the upper portion is in contact with the oxide layer.
3 . The semiconductor structure of claim 2 , wherein the upper portion extends from the sidewall portion and away from the semiconductor device.
4 . The semiconductor structure of claim 1 , wherein an angle between the bottom portion and the sidewall portion is greater than 90°.
5 . The semiconductor structure of claim 1 , further comprising: a semiconductor material layer disposed between the first isolation layer and the semiconductor device.
6 . The semiconductor structure of claim 1 , further comprising: a second isolation layer disposed under the capacitor structure, wherein the capacitor structure is disposed between the first isolation layer and the second isolation layer.
7 . The semiconductor structure of claim 1 , wherein the capacitor structure includes a first electrode layer, a second electrode layer over the first electrode layer, and a dielectric between the first electrode layer and the second electrode layer.
8 . The semiconductor structure of claim 7 , further comprising: a first contact electrically connected to the first electrode layer; and a second contact electrically connected to the second electrode layer, wherein the first contact and the second contact extend through the oxide layer.
9 . The semiconductor structure of claim 8 , further comprising: an isolation structure coupled to the first electrode layer and extending through the dielectric and the second electrode layer, wherein the isolation structure surrounds the first contact.
10 . A semiconductor structure, comprising: a substrate having a surface; a capacitor structure disposed within the substrate and having a bottom portion, a sidewall portion disposed over and coupled to the bottom portion, and an upper portion coupled to the sidewall portion and exposed through the surface; and a semiconductor device disposed over and separated from the capacitor structure; wherein the sidewall portion is disposed between the bottom portion and the upper portion, and at least a portion of the semiconductor device is surrounded by the sidewall portion of the capacitor structure from a plan view.
11 . The semiconductor structure of claim 10 , further comprising: a first isolation layer disposed under the capacitor structure; and a second isolation layer disposed over the capacitor structure and between the capacitor structure and the semiconductor device, wherein the capacitor structure is disposed between the first isolation layer and the second isolation layer.
12 . The semiconductor structure of claim 10 , wherein the capacitor structure comprises a first electrode layer and a second electrode layer separated from the first electrode layer, and the first electrode layer and the second electrode layer comprise metal silicide.
13 . The semiconductor structure of claim 10 , further comprising: a semiconductor material layer disposed between the capacitor structure and the semiconductor device, wherein the capacitor structure surrounds the semiconductor material layer from the plan view, and the semiconductor material layer surrounds the portion of the semiconductor device from the plan view.
14 . A method of manufacturing a semiconductor structure, comprising: providing a substrate having a surface; forming a recess in the substrate on the surface; forming a capacitor structure within and conformal to the recess; forming a first isolation layer in the recess and over the capacitor structure; disposing a semiconductor material layer in the recess and over the first isolation layer; and forming a semiconductor device over the semiconductor material layer, wherein at least a portion of the semiconductor device is surrounded by the capacitor structure.
15 . The method of claim 14 , further comprising: planarizing the semiconductor material layer, the capacitor structure and the substrate before the formation of the semiconductor device, wherein a top surface of the semiconductor material layer is coplanar with the surface of the substrate.
16 . The method of claim 14 , further comprising: forming a second isolation layer in the recess, wherein the capacitor structure is formed between the second isolation layer and the first isolation layer.
17 . The method of claim 14 , wherein the formation of the capacitor structure includes: forming a first doped layer in the recess; forming a second doped layer on the first doped layer; forming a third doped layer over the second doped layer; and annealing the substrate to transfer the first doped layer to a first electrode layer, the second doped layer to a dielectric, and the third doped layer to a second electrode layer.
18 . The method of claim 14 , further comprising: forming a first isolation structure surrounded by the capacitor structure; forming a second isolation structure coupled to the capacitor structure; and electrically coupling a first contact to the capacitor structure, wherein the first isolation structure is disposed between the capacitor structure and the semiconductor device, and a portion of the first contact is surrounded by the second isolation structure.
19 . The method of claim 14 , wherein the formation of the semiconductor device includes disposing an oxide layer over the capacitor structure, the first isolation layer, the semiconductor material layer and the surface of the substrate.
20 . The method of claim 14 , wherein the formation of the capacitor structure includes: forming a bottom portion within the recess; and forming a sidewall portion disposed over and coupled to the bottom portion within the recess, wherein the bottom portion and the sidewall portion are formed simultaneously.

Description

BACKGROUND The semiconductor industry has experienced rapid growth due to ongoing improvements in integration density of a variety of electrical components. To accommodate the miniaturized scale of semiconductor devices, various technologies and applications have been developed for wafer-level packaging, involving greater numbers of different components with different functions. Improvements in integration density have resulted from iterative reduction of minimum feature size, allowing more components to be integrated into a given area. Such advances require the semiconductor devices to undergo ever-greater numbers of manufacturing processes. As semiconductor technologies further advance, embedding of electrical components into a semiconductive substrate has emerged as an effective approach to further reducing a physical size of a semiconductor device. The electrical component is at least partially embedded within the semiconductive substrate in order to minimize an amount of space occupied above the semiconductive substrate. Such embedding processes utilize sophisticated techniques, and improvements are desired. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 2 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 3 is a schematic cross-sectional view taken along a line A-A′ in FIG. 1 or FIG. 2. FIG. 4 is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 5 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 6 is a schematic cross-sectional view taken along a line B-B′ in FIG. 5. FIG. 7A is a schematic cross-sectional view of a semiconductor structure according to aspects of the present disclosure in some embodiments. FIGS. 7B, 8 and 9 are schematic top views of a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 10 is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 11 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 12 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. FIGS. 13 to 31 are cross-sectional views of one or more stages of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, although the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, comp