US-20260129890-A1 - SEMICONDUCTOR DEVICE

US20260129890A1US 20260129890 A1US20260129890 A1US 20260129890A1US-20260129890-A1

Abstract

A semiconductor device includes, within an outer peripheral region: an outer peripheral p-type layer; an outer peripheral n-type layer positioned on an outer peripheral side relative to the outer peripheral p-type layer with a space from the outer peripheral p-type layer; a high breakdown voltage p-type layer arranged to include a portion of an upper surface of a semiconductor substrate located between the outer peripheral p-type layer and the outer peripheral n-type layer; a drift n-type layer extending up to the upper surface between the high breakdown voltage p-type layer and the outer peripheral n-type layer; a protective electrode disposed above the high breakdown voltage p-type layer via an interlayer insulating film and electrically connected to an upper electrode; and a semi-insulating film covering the upper surface between the protective electrode and the outer peripheral n-type layer and having a resistivity of 1×10 8 Ω·cm to 1×10 14 Ω·cm at 25° C.

Inventors

Kosuke Ota
Masakiyo Sumitomo
Shigeki Takahashi

Assignees

DENSO CORPORATION

Dates

Publication Date: 20260507
Application Date: 20251230
Priority Date: 20230703

Claims (5)

1 . A semiconductor device comprising: a semiconductor substrate having an upper surface and a lower surface; an upper electrode disposed in contact with the upper surface of the semiconductor substrate; a lower electrode disposed in contact with the lower surface of the semiconductor substrate; a protective electrode electrically connected to the upper electrode; and a semi-insulating film having a resistivity of greater than or equal to 1×10 8 Ω·cm and less than or equal to 1×10 14 Ω·cm at 25° C., wherein the semiconductor substrate has: an element region located below a contact portion between the upper electrode and the upper surface; and an outer peripheral region located between the element region and an outer peripheral end face of the semiconductor substrate, the semiconductor substrate includes: an element p-type layer disposed within the element region and in contact with the upper electrode; an outer peripheral p-type layer disposed within the outer peripheral region, arranged to include the upper surface, and in contact with the element p-type layer; an outer peripheral n-type layer disposed within the outer peripheral region, arranged to include the upper surface, and positioned on an outer peripheral side relative to the outer peripheral p-type layer with a space from the outer peripheral p-type layer; a high breakdown voltage p-type layer disposed within the outer peripheral region, arranged to include a portion of the upper surface located between the outer peripheral p-type layer and the outer peripheral n-type layer; and a drift n-type layer extending from a position below the element p-type layer to a position below the outer peripheral n-type layer, having an n-type impurity concentration lower than an n-type impurity concentration of the outer peripheral n-type layer, and extending up to the upper surface between the high breakdown voltage p-type layer and the outer peripheral n-type layer, the protective electrode is disposed above the high breakdown voltage p-type layer via an interlayer insulating film, and the semi-insulating film covers the upper surface between the protective electrode and the outer peripheral n-type layer, and electrically connects the protective electrode and the outer peripheral n-type layer.
2 . The semiconductor device according to claim 1 , wherein the high breakdown voltage p-type layer is in contact with the outer peripheral p-type layer, is shallower than the outer peripheral p-type layer, and has a p-type impurity concentration lower than a p-type impurity concentration of the outer peripheral p-type layer, and an outer peripheral end of the protective electrode is positioned on an inner peripheral side relative to an outer peripheral end of the high breakdown voltage p-type layer.
3 . The semiconductor device according to claim 2 , wherein the outer peripheral end of the protective electrode is positioned on the inner peripheral side relative to an inner peripheral end of a depletion layer that is formed within the high breakdown voltage p-type layer when a rated voltage is applied between the upper electrode and the lower electrode at 25° C.
4 . The semiconductor device according to claim 1 , wherein a thickness of the semi-insulating film decreases from an inner peripheral side toward the outer peripheral side.
5 . The semiconductor device according to claim 1 , wherein the resistivity of the semi-insulating film increases from an inner peripheral side toward the outer peripheral side.

Description

CROSS REFERENCE TO RELATED APPLICATIONS The present application is a continuation application of International Patent Application No. PCT/JP2024/015415 filed on Apr. 18, 2024, which designated the U.S. and claims the benefit of priority from Japanese Patent Application No. 2023-109289 filed on Jul. 3, 2023. The entire disclosures of all of the above applications are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a semiconductor device. BACKGROUND Conventionally, semiconductor devices having an element region provided with a semiconductor element and an outer peripheral region disposed around the element region have been known. SUMMARY A semiconductor device according to one aspect of the present disclosure includes: a semiconductor substrate having an upper surface and a lower surface; an upper electrode disposed in contact with the upper surface of the semiconductor substrate; a lower electrode disposed in contact with the lower surface of the semiconductor substrate; a protective electrode electrically connected to the upper electrode; and a semi-insulating film having a resistivity of greater than or equal to 1×108 Ω·cm and less than or equal to 1×1014 Ω·cm at 25° C. The semiconductor substrate has an element region located below a contact portion between the upper electrode and the upper surface, and an outer peripheral region located between the element region and an outer peripheral end face of the semiconductor substrate. The semiconductor substrate includes: an element p-type layer disposed within the element region and in contact with the upper electrode; an outer peripheral p-type layer disposed within the outer peripheral region, arranged to include the upper surface, and in contact with the element p-type layer; an outer peripheral n-type layer disposed within the outer peripheral region, arranged to include the upper surface, and positioned on an outer peripheral side relative to the outer peripheral p-type layer with a space from the outer peripheral p-type layer; a high breakdown voltage p-type layer disposed within the outer peripheral region, arranged to include a portion of the upper surface located between the outer peripheral p-type layer and the outer peripheral n-type layer; and a drift n-type layer extending from a position below the element p-type layer to a position below the outer peripheral n-type layer, having an n-type impurity concentration lower than an n-type impurity concentration of the outer peripheral n-type layer, and extending up to the upper surface between the high breakdown voltage p-type layer and the outer peripheral n-type layer. The protective electrode may be disposed above the high breakdown voltage p-type layer via an interlayer insulating film. The semi-insulating film may cover the upper surface between the protective electrode and the outer peripheral n-type layer, and may electrically connect the protective electrode and the outer peripheral n-type layer. BRIEF DESCRIPTION OF DRAWINGS Objects, features and advantages of the present disclosure will become apparent from the following detailed description made with reference to the accompanying drawings. In the drawings: FIG. 1 is a plan view of a semiconductor device according to an embodiment as seen from above; FIG. 2 is a cross-sectional view of the semiconductor device taken along line II-II in FIG. 1; FIG. 3 is a diagram showing a potential distribution when a rated voltage is applied at room temperature to the semiconductor device according to the embodiment; FIG. 4 is a diagram showing a potential distribution when a rated voltage is applied at room temperature to a semiconductor device of a comparative example; FIG. 5 is a diagram showing a potential distribution when the rated voltage is applied at a high temperature to the semiconductor device according to the embodiment; FIG. 6 is a diagram showing a potential distribution when the rated voltage is applied at a high temperature to the semiconductor device of the comparative example; FIG. 7 is a cross-sectional view of a semiconductor device according to a first modification; FIG. 8 is a cross-sectional view of a semiconductor device according to a second modification; and FIG. 9 is a cross-sectional view of a semiconductor device according to a third modification. DETAILED DESCRIPTION Next, relevant technology is described to facilitate understanding of the following embodiments. A semiconductor device includes an element region provided with a semiconductor element, and an outer peripheral region disposed around the element region. The outer peripheral region has a high breakdown voltage structure such as a reduced surface field (RESURF) layer or a guard ring. In the semiconductor device, a surface of the semiconductor substrate within the outer peripheral region is covered with a semi-insulating film. Furthermore, in the semiconductor device, an n+-type semiconductor region is disposed on an outer peripheral