US-20260129891-A1 - SEMICONDUCTOR DEVICE

Abstract

A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a dummy fin structure, a mask layer, a first source/drain contact, and an isolation plug. The gate structure crosses the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer. The dummy fin structure is in contact with the first source/drain epitaxial structure. The mask layer is over the dummy fin structure. The first source/drain contact is over and electrically connected to the first source/drain epitaxial structure. The isolation plug is over the mask layer and in contact with the first source/drain contact. The isolation plug is directly over the first source/drain contact and the mask layer.

Inventors

• Chun-Yuan Chen
• Meng-Huan Jao
• Huan-Chieh Su
• Cheng-Chi Chuang
• Chih-Hao Wang

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20251230

Claims (20)

1. 1 . A device comprising: a channel layer; a gate structure crossing the channel layer and comprising a gate dielectric layer and at least one metal layer; a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite sides of the channel layer, wherein a thickness of the first source/drain epitaxial structure is different from a width of the first source/drain epitaxial structure in a cross-sectional view; a dummy fin structure in contact with the first source/drain epitaxial structure; a mask layer over the dummy fin structure; a first source/drain contact over and electrically connected to the first source/drain epitaxial structure; and an isolation plug over the mask layer and in contact with the first source/drain contact, wherein the isolation plug is directly over the first source/drain contact and the mask layer.
2. 2 . The device of claim 1 , wherein the isolation plug comprises: a first portion directly on the mask layer; and a second portion directly on the first source/drain contact, wherein the first portion and the second portion have different thicknesses.
3. 3 . The device of claim 2 , wherein a bottom surface of the first portion of the isolation plug is lower than a topmost surface of the mask layer.
4. 4 . The device of claim 2 , wherein the first portion of the isolation plug is partially embedded in the mask layer.
5. 5 . The device of claim 1 , further comprising a contact spacer lining a sidewall of the mask layer.
6. 6 . The device of claim 5 , wherein the first source/drain contact is separated from the mask layer by the contact spacer.
7. 7 . The device of claim 5 , wherein a top surface of the contact spacer is lower than a topmost surface of the mask layer.
8. 8 . The device of claim 1 , further comprising a second source/drain contact in contact with the isolation plug, wherein the first source/drain contact is separated from the second source/drain contact by the isolation plug.
9. 9 . The device of claim 8 , wherein the second source/drain contact is in contact with a topmost surface of the mask layer.
10. 10 . A device comprising: a first source/drain epitaxial structure and a second source/drain epitaxial structure spaced apart from each other; a semiconductor layer between the first source/drain epitaxial structure and the second source/drain epitaxial structure; a gate structure covering the semiconductor layer; a source/drain contact over the first source/drain epitaxial structure; a metal alloy layer between the source/drain contact and the first source/drain epitaxial structure and comprising a curved profile, wherein an electrical conductivity of the metal alloy layer is greater than an electrical conductivity of the first source/drain epitaxial structure; an isolation plug in contact with a sidewall of the source/drain contact; and a contact spacer, comprising: a first portion lining a sidewall of the isolation plug and having a first thickness, wherein a bottom surface of the first portion is higher than a bottom surface of the isolation plug in a cross-sectional view; and a second portion lining a sidewall of the source/drain contact and having a second thickness greater than the first thickness in a top view.
11. 11 . The device of claim 10 , wherein the semiconductor layer extends in a first direction, and a width of the isolation plug in the first direction is greater than a width of the source/drain contact in the first direction.
12. 12 . The device of claim 10 , wherein the source/drain contact is in contact with the bottom surface of the isolation plug.
13. 13 . The device of claim 10 , wherein a portion of the isolation plug is directly above the metal alloy layer.
14. 14 . The device of claim 10 , wherein a portion of the source/drain contact is sandwiched between the metal alloy layer and the isolation plug.
15. 15 . A device comprising: a semiconductor structure; a first isolation structure and a second isolation structure on opposite sides of the semiconductor structure, wherein a top surface of the first isolation structure is non-planar in a cross-sectional view; a channel structure over the semiconductor structure; a gate structure wrapping around the channel structure; a first source/drain structure and a second source/drain structure on opposite sides of the gate structure and connected to the channel structure and the semiconductor structure; a first mask layer over the first isolation structure; a second mask layer over the second isolation structure; a first dielectric structure over the first mask layer; a source/drain contact over the first source/drain structure and between the first mask layer and the second mask layer, wherein the source/drain contact is in contact with the first dielectric structure, and a portion of the source/drain contact and a portion of the first dielectric structure are directly over the first mask layer; and a contact spacer between the gate structure and the source/drain contact.
16. 16 . The device of claim 15 , further comprising a second dielectric structure over the second mask layer and the source/drain contact.
17. 17 . The device of claim 15 , wherein the source/drain contact is in contact with a top surface of the first mask layer.
18. 18 . The device of claim 15 , wherein an interface between the first mask layer and the source/drain contact is higher than an interface between the first mask layer and the first dielectric structure.
19. 19 . The device of claim 15 , further comprising a contact etch stop layer between the source/drain contact and the first source/drain structure, wherein the source/drain contact covers the contact etch stop layer.
20. 20 . The device of claim 15 , wherein the source/drain contact comprises a top portion and a bottom portion between the top portion and the first source/drain structure, wherein a sidewall of the top portion of the source/drain contact is misaligned with a sidewall of the bottom portion of the source/drain contact.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application is a divisional application of the U.S. application Ser. No. 17/742,265, filed May 11, 2022, which is hereby incorporated by reference in its entirety. BACKGROUND The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1-23E illustrate a method for manufacturing a semiconductor device (or an integrated circuit structure) at various stages in accordance with some embodiments of the present disclosure. FIG. 23F is an enlarged view of area F in FIG. 23D. FIG. 23G is an enlarged view of area G in FIG. 23A. FIG. 23H is an enlarged view of area H in FIG. 23B. FIG. 23I is an enlarged view of area I in FIG. 23C. FIG. 24 is a cross-sectional view of a semiconductor device (or an integrated circuit structure) in accordance with some embodiments of the present disclosure. FIG. 25 is a cross-sectional view of a semiconductor device (or an integrated circuit structure) in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, “around,” “about,” “approximately,” or “substantially” shall generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around,” “about,” “approximately,” or “substantially” can be inferred if not expressly stated. One of ordinary skill in the art will appreciate that the dimensions may be varied according to different technology nodes. One of ordinary skill in the art will recognize that the dimensions depend upon the specific device type, technology generation, minimum feature size, and the like. It is intended, therefore, that the term be interpreted in light of the technology being evaluated. As used herein, the term “etch selectivity” refers to the ratio of the etch rates of two different materials under the same etching conditions. As used herein, the term “high-k” refers to a high dielectric constant. In the field of semiconductor device structures and manufacturing processes, high-k refers to a dielectric constant that is greater than the dielectric constant of SiO2 (e.g., greater than 3.9). As used herein, the term “low-k” refers to a low dielectric constant. In the field of semiconductor device structures and manufacturing processes, low-k refers to a dielectric constant that is less than the dielectric constant of SiO2 (e.g., less than 3.9). As us