US-20260129892-A1 - SEMICONDUCTOR DEVICE INCLUDING ACTIVE FIN

Abstract

A semiconductor device includes a semiconductor structure including an active fin extending from a substrate, extending in a first direction and having a first region and a second region, a gate structure intersecting the first region of the active fin and extending in a second direction, and source/drain regions on the second region of the active fin. The second region of the active fin comprises an upper surface and a lower portion below the upper surface in a third direction, the first region of the active fin has a first width in the second direction, the upper surface of the second region of the active fin has a second width in the second direction, the lower portion of the second region of the active fin has a third width in the second direction, and the second width is different from the first width and the third width.

Inventors

• Keunhwi Cho
• Jinkyu Kim
• Myunggil Kang
• Dongwon Kim
• Kisung Suh

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20251229

Priority Date

20211026

Claims (20)

1. 1 . A semiconductor device comprising: a semiconductor structure including an active fin extending from a substrate, extending in a first direction and having a first region and a second region; a device separation layer on portions of side surfaces of the active fin; a gate structure intersecting the first region of the active fin and extending in a second direction substantially perpendicular to the first direction, and including a gate electrode; and source/drain regions on the second region of the active fin, wherein the second region of the active fin comprises an upper surface and a lower portion below the upper surface in a third direction that is substantially perpendicular to an upper surface of the substrate, the first region of the active fin has a first width in the second direction, the upper surface of the second region of the active fin has a second width in the second direction, the lower portion of the second region of the active fin has a third width in the second direction, and the second width is different from the first width and the third width.
2. 2 . The semiconductor device according to claim 1 , wherein the active fin includes a recess portion between the upper surface and the lower portion of the second region.
3. 3 . The semiconductor device according to claim 2 , further comprising: an insulating liner on the device separation layer, the recess portion of the active fin and the source/drain regions.
4. 4 . The semiconductor device according to claim 3 , wherein the recess portion of the active fin is in contact with the insulating liner.
5. 5 . The semiconductor device according to claim 3 , further comprising: a spacer between the recess portion of the active fin and the insulating liner.
6. 6 . The semiconductor device according to claim 1 , wherein the upper surface of the second region of the active fin has a downwardly concave shape in the third direction.
7. 7 . The semiconductor device according to claim 1 , wherein the second region of the active fin comprises a first portion in contact with the device separation layer and a second portion extending from the first portion and protruding upwardly relative to the device separation layer, and a slope of a side surface of the first portion is different from a slope of a side surface of the second portion.
8. 8 . The semiconductor device according to claim 1 , wherein a width of the source/drain regions in the second direction is greater than the second width and the third width of the active fin.
9. 9 . The semiconductor device according to claim 1 , wherein a width of the source/drain regions in the second direction is greater than the first width of the active fin.
10. 10 . The semiconductor device according to claim 1 , wherein the semiconductor structure includes channel layers disposed on the first region of the active fin and spaced apart from each other in the third direction, and the gate structure includes a gate dielectric layer between the channel layers and the gate electrode, and a gate spacer disposed on side surfaces of the gate electrode.
11. 11 . The semiconductor device according to claim 10 , wherein at least a portion of the active fin, which overlaps the gate spacer of the gate structure in the third direction, has a width in the second direction that is approximately the same as the second width of the active fin.
12. 12 . The semiconductor device according to claim 1 , further comprising: contact structures disposed on the source/drain regions and connecting to the source/drain regions.
13. 13 . A semiconductor device comprising: an active fin extending from a substrate, extending in a first direction and having a first region and a second region; channel layers disposed on the first region of the active fin and spaced apart from each other in a direction substantially perpendicular to an upper surface of the substrate; a gate structure intersecting the first region of the active fin and extending in a second direction substantially perpendicular to the first direction, and including a gate electrode disposed between the channel layers and a gate dielectric layer between the gate electrode and the channel layers; and source/drain regions on the second region of the active fin and connecting to the channel layers, wherein the first region of the active fin has a first width in the second direction, an upper surface of the second region of the active fin has a second width in the second direction, a lower portion of the second region of the active fin has a third width in the second direction, the second width is different from the first width and the third width, and the active fin includes a recess portion between the upper surface of the second region and the lower portion of the second region.
14. 14 . The semiconductor device according to claim 13 , further comprising: a device separation layer on portions of side surfaces of the active fin; and an insulating liner on the device separation layer, the recess portion of the active fin and the source/drain regions.
15. 15 . The semiconductor device according to claim 14 , wherein the recess portion of the active fin is in contact with the insulating liner.
16. 16 . The semiconductor device according to claim 14 , further comprising: a spacer between the recess portion of the active fin and the insulating liner.
17. 17 . The semiconductor device according to claim 13 , further comprising: inner spacers between the channel layers, wherein side surfaces of the inner spacers are substantially coplanar with side surfaces of the channel layers.
18. 18 . The semiconductor device according to claim 13 , wherein the gate dielectric layer has a recessed side surface covering side surfaces of the gate electrode between the channel layers, and the source/drain regions are in contact with the recessed side surface of the gate dielectric layer.
19. 19 . A semiconductor device comprising: a first semiconductor structure and a second semiconductor structure extending in a first direction on an NMOS region and a PMOS region of a substrate, respectively; gate structures intersecting the first semiconductor structure and the second semiconductor structure, and extending in a second direction substantially perpendicular to the first direction; and source/drain regions disposed on each of the first semiconductor structure and the second semiconductor structure and disposed between the gate structures, wherein each of the first semiconductor structure and the second semiconductor structure includes an active fin extending in the first direction and including a first region and a second region, the source/drain regions are disposed on the second region of the active fin, the second region of the active fin comprises an upper surface and a lower portion below the upper surface in a third direction that is substantially perpendicular to an upper surface of the substrate, the first region of the active fin has a first width in the second direction, the upper surface of the second region of the active fin has a second width in the second direction, the lower portion of the second region of the active fin has a third width in the second direction, and the second width is different from the first width and the third width.
20. 20 . The semiconductor device according to claim 19 , wherein the active fin includes a recess portion between the upper surface and the lower portion of the second region.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This Application is a Continuation of U.S. application Ser. No. 17/863,741, filed Jul. 13, 2022, entitled “METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES”. Foreign priority benefits are claimed under 35 U.S.C. § 119(a)-(d) or 35 U.S.C. § 365(b) of South Korean application number 10-2021-0143382, filed Oct. 26, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND The present disclosure relates to methods of manufacturing semiconductor devices. As demand for high performance, high speed, and/or multifunctionality of a semiconductor device increases, the degree of integration of semiconductor devices has increased. It may be beneficial to implement patterns having a fine width or a fine distance in manufacturing a semiconductor device having a fine pattern corresponding to the trend of high integration of semiconductor devices. In addition, in order to overcome the limitations of operating characteristics due to a reduction in size of planar metal oxide semiconductor field effect transistors (MOSFETs), efforts have been made to develop semiconductor devices including FinFETs having a three-dimensional channel structure. SUMMARY An aspect of the present disclosure is to provide semiconductor devices having improved electrical characteristics and reliability characteristics, and methods for manufacturing the same. According to an aspect of the present disclosure, a semiconductor device comprises a semiconductor structure including an active fin extending from a substrate, extending in a first direction and having a first region and a second region, a device separation layer on portions of side surfaces of the active fin, a gate structure intersecting the first region of the active fin and extending in a second direction perpendicular to the first direction, and including a gate electrode, and source/drain regions on the second region of the active fin, wherein the second region of the active fin comprises an upper surface and a lower portion below the upper surface in a third direction that is perpendicular to an upper surface of the substrate, the first region of the active fin has a first width in the second direction, the upper surface of the second region of the active fin has a second width in the second direction, the lower portion of the second region of the active fin has a third width in the second direction, and the second width is different from the first width and the third width. According to another aspect of the present disclosure, a semiconductor device comprises an active fin extending from a substrate, extending in a first direction and having a first region and a second region, channel layers disposed on the first region of the active fin and spaced apart from each other in a direction perpendicular to an upper surface of the substrate, a gate structure intersecting the first region of the active fin and extending in a second direction perpendicular to the first direction, and including a gate electrode disposed between the channel layers and a gate dielectric layer between the gate electrode and the channel layers, and source/drain regions on the second region of the active fin and connecting to the channel layers, wherein the first region of the active fin has a first width in the second direction, an upper surface of the second region of the active fin has a second width in the second direction, a lower portion of the second region of the active fin has a third width in the second direction, the second width is different from the first width and the third width, and the active fin includes a recess portion between the upper surface of the second region and the lower portion of the second region. According to another aspect of the present disclosure, a semiconductor device comprises a first semiconductor structure and a second semiconductor structure extending in a first direction on an NMOS region and a PMOS region of a substrate, respectively, gate structures intersecting the first semiconductor structure and the second semiconductor structure, and extending in a second direction perpendicular to the first direction, and source/drain regions disposed on each of the first semiconductor structure and the second semiconductor structure and disposed between the gate structures, wherein each of the first semiconductor structure and the second semiconductor structure includes an active fin extending in the first direction and including a first region and a second region, the source/drain regions are disposed on the second region of the active fin, the second region of the active fin comprises an upper surface and a lower portion below the upper surface in a third direction that is perpendicular to an upper surface of the substrate, the first region of the active fin has a first width in the second direction, the upper surface of the second region of the active fin has a se