US-20260129894-A1 - INTERFACIAL LAYER IN SEMICONDUCTOR DEVICES

Abstract

This disclosure is directed to a method of improving a quality of an interfacial layer of a gate structure of a semiconductor device. The method includes forming a channel region on a substrate and oxidizing a surface of the channel region to form the interfacial layer including silicon oxide. The method further includes depositing a layer of metal oxide (e.g., yttrium oxide) on the interfacial layer, performing an annealing process to transform silicon oxide in the interfacial layer into silicon dioxide by reducing a density of oxygen vacancies in the interfacial layer, and removing the layer of metal oxide. The method further includes forming a high-k dielectric layer and a gate electrode on the interfacial layer to form the gate structure.

Inventors

• Shen-Yang LEE
• Hsiang-Pi Chang
• Chun-Fu Lu
• HUANG-LIN CHAO
• Pinyen Lin
• Hsu-Kai Chang
• Kenichi Sano

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20241101

Claims (20)

1. 1 . A method, comprising: forming a channel region in a fin structure on a substrate; forming a source/drain (S/D) region adjacent to the channel region; forming an interfacial layer (IL) on the channel region, wherein forming the IL comprises: forming a layer of silicon oxide on the channel region; depositing a layer of yttrium oxide on the layer of silicon oxide; annealing the layer of yttrium oxide and the layer of silicon oxide to reduce a density of oxygen vacancies in the layer of silicon oxide; and removing the layer of yttrium oxide; depositing a high-k dielectric layer on the IL; and depositing a gate electrode on the high-k dielectric layer.
2. 2 . The method of claim 1 , wherein annealing the layer of yttrium oxide and the layer of silicon oxide comprises forming a layer of silicate between the layer of yttrium oxide and the layer of silicon oxide.
3. 3 . The method of claim 2 , wherein forming the IL further comprises removing the layer of silicate after removing the layer of yttrium oxide.
4. 4 . The method of claim 1 , wherein annealing the layer of yttrium oxide and the layer of silicon oxide comprises transforming the layer of silicon oxide into a layer of silicon dioxide.
5. 5 . The method of claim 1 , wherein annealing the layer of yttrium oxide and the layer of silicon oxide comprises increasing a ratio of oxygen to silicon in the IL.
6. 6 . The method of claim 1 , wherein depositing the layer of yttrium oxide comprises depositing the layer of yttrium oxide by an atomic layer deposition process.
7. 7 . The method of claim 1 , wherein forming the layer of silicon oxide comprises forming the layer of silicon oxide using a chemical solution of deionized water (DI-water), carbonated DI-water (DICO 2 ), ozonated DI-water (DIO 3 ), hydrogen peroxide (H 2 O 2 ), sulfuric acid (H 2 SO 4 ), chloric acid (HCl), or ammonia (NH 4 OH).
8. 8 . A method, comprising: forming a nanostructure in a fin structure; forming a source/drain (S/D) region adjacent to the nanostructure; and forming a gate structure surrounding the nanostructure, wherein forming the gate structure comprises: forming, on the nanostructure, an interfacial layer (IL) comprising oxygen and silicon; increasing a ratio of oxygen to silicon in the IL; depositing a high-k dielectric layer on the IL; and depositing a gate electrode on the high-k dielectric layer.
9. 9 . The method of claim 8 , wherein increasing the ratio of oxygen to silicon in the IL comprises: depositing a layer of yttrium oxide on the IL; annealing the layer of yttrium oxide and the IL; and removing the layer of yttrium oxide.
10. 10 . The method of claim 9 , wherein annealing the layer of yttrium oxide and the IL comprises forming a layer of silicate between the layer of yttrium oxide and the IL.
11. 11 . The method of claim 8 , wherein increasing the ratio of oxygen to silicon in the IL comprises reducing a thickness of the IL.
12. 12 . The method of claim 11 , wherein reducing the thickness of the IL comprises reducing the thickness of the IL by about 5% to about 20%.
13. 13 . The method of claim 8 , wherein increasing the ratio of oxygen to silicon in the IL comprises removing oxygen vacancies in the IL.
14. 14 . The method of claim 8 , wherein increasing the ratio of oxygen to silicon in the IL comprises increasing the ratio of oxygen to silicon in the IL to about 2:1.
15. 15 . A structure, comprising: a substrate; a fin structure on the substrate, wherein the fin structure comprises a channel region; a source/drain (S/D) region on the fin structure and adjacent to the channel region; and a gate structure surrounding the channel region, wherein the gate structure comprises: an interfacial layer (IL) on the channel region, wherein the IL comprises silicon dioxide, wherein a ratio of oxygen to silicon in the IL is about 2:1; a high-k dielectric layer on the IL; a work function layer on the high-k dielectric layer; and a gate electrode on the work function layer.
16. 16 . The structure of claim 15 , wherein the IL is in contact with top, bottom, and side surfaces of the channel region.
17. 17 . The structure of claim 15 , wherein a thickness of the IL is about 1 nm.
18. 18 . The structure of claim 15 , wherein the IL comprises yttrium, scandium, lanthanum, zinc, or lutetium.
19. 19 . The structure of claim 15 , further comprising an oxide layer on the S/D region, wherein thicknesses of the oxide layer and the IL are substantially the same.
20. 20 . The structure of claim 15 , further comprising an oxide layer on the S/D region, wherein another ratio of oxygen to silicon in the oxide layer is about 2:1.

Description

BACKGROUND With advances in semiconductor technology, there has been increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the dimensions of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finFETs), and gate-all-around field effect transistors (GAA FETs). Such scaling down has increased the complexity of semiconductor manufacturing processes. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the common practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of illustration and discussion. FIG. 1 is an isometric view of a semiconductor device including semiconductor transistors, in accordance with some embodiments. FIG. 2 is a cross-sectional view of a semiconductor device including semiconductor transistors, in accordance with some embodiments. FIG. 3 is an x-ray photoelectron spectroscopy (XPS) diagram of an interfacial layer of a semiconductor transistor, in accordance with some embodiments. FIGS. 4A and 4B are flowcharts of a method for the formation of a semiconductor transistor, in accordance with some embodiments. FIGS. 5 and 6 are isometric views of intermediate structures during the fabrication of a semiconductor transistor, in accordance with some embodiments. FIGS. 7-19 are cross-sectional views of intermediate structures during the fabrication of a semiconductor transistor, in accordance with some embodiments. Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and/or structurally similar elements. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed that are between the first and second features, such that the first and second features are not in direct contact. As used herein, the formation of a first feature on a second feature means the first feature is formed in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. It is to be understood that the terms “about” and “substantially” can refer to a percentage of the values as interpreted by those skilled in relevant art(s) in light of the teachings herein. It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described. It is to be understood that the phraseology or terminology herein is for the