US-20260129897-A1 - FABRICATION METHOD OF HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE

US20260129897A1US 20260129897 A1US20260129897 A1US 20260129897A1US-20260129897-A1

Abstract

A method of fabrication a high electron mobility transistor structure includes the following steps. A compound semiconductor channel layer is formed on a substrate. A compound semiconductor barrier layer is formed on the compound semiconductor channel layer. A compound semiconductor cap layer is formed on the compound semiconductor barrier layer. The compound semiconductor cap layer includes a first segment and a second segment arranged along a first direction, and a first gap is between the first segment and the second segment. A gate electrode is formed on the compound semiconductor cap layer. A source electrode and a drain electrode are formed on the compound semiconductor barrier layer. The source electrode and the drain electrode are arranged along a second direction, and respectively located on two opposite sides of the compound semiconductor cap layer.

Inventors

Shin-Cheng Lin
Chia-Ching HUANG

Assignees

VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION

Dates

Publication Date: 20260507
Application Date: 20251222

Claims (5)

1 . A method of fabricating a high electron mobility transistor (HEMT) structure, comprising: forming a compound semiconductor channel layer on a substrate; forming a compound semiconductor barrier layer on the compound semiconductor channel layer; forming a compound semiconductor cap layer on the compound semiconductor barrier layer, wherein the compound semiconductor cap layer comprises a first segment and a second segment arranged along a first direction, and a first gap between the first segment and the second segment; forming a gate electrode on the compound semiconductor cap layer; and forming a source electrode and a drain electrode on the compound semiconductor barrier layer, wherein the source electrode and the drain electrode are arranged along a second direction and respectively located on two sides of the compound semiconductor cap layer.
2 . The method of claim 1 , wherein forming the compound semiconductor cap layer comprises: epitaxially growing a compound semiconductor material layer on the compound semiconductor barrier layer; forming a patterned photoresist on the compound semiconductor material layer, wherein the patterned photoresist has an opening corresponding to a predetermined region of the first gap; and etching away a portion of the compound semiconductor material layer not covered by the patterned photoresist to form the first segment, the second segment and the first gap.
3 . The method of claim 1 , wherein forming the compound semiconductor cap layer further comprises forming a first connecting portion between the first segment and the second segment, and the thickness of the first connecting portion is less than the respective thicknesses of the first segment and the second segment.
4 . The method of claim 3 , wherein forming the first connecting portion comprises: epitaxially growing a compound semiconductor material layer on the compound semiconductor barrier layer; forming a patterned photoresist on the compound semiconductor material layer, wherein the patterned photoresist has an opening corresponding to a predetermined region of the first gap; etching away a portion of the compound semiconductor material layer not covered by the patterned photoresist to form the first segment, the second segment and the first gap; and epitaxially growing a compound semiconductor material in the first gap to form the first connecting portion.
5 . The method of claim 3 , wherein forming the first connecting portion comprises: epitaxially growing a compound semiconductor material layer on the compound semiconductor barrier layer; forming a first patterned photoresist on the compound semiconductor material layer; etching away a portion of the compound semiconductor material layer not covered by the first patterned photoresist to form a patterned compound semiconductor material block; forming a second patterned photoresist on the patterned compound semiconductor material block, wherein the second patterned photoresist has an opening corresponding to a predetermined region of the first gap; and etching away an upper portion of the patterned compound semiconductor material block exposed through the opening to form the first connecting portion.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is a division of U.S. application Ser. No. 18/098,079, filed on Jan. 17, 2023. The content of the application is incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention The present disclosure relates generally to a fabrication method of semiconductor devices, and more particularly to a fabrication method of a high electron mobility transistor (HEMT) structure integrating an enhancement-mode HEMT and a depletion-mode HEMT. 2. Description of the Prior Art In the applications of AC/DC power converters and drivers, junction field-effect transistors (JFETs) or depletion-mode field-effect transistors (D-mode FETs) are usually used to provide start-up function. However, the conventional JFETs require a well region to pinch-off the voltage, and the well region is most likely varied by the fabrication process, which easily leads to a shift in the pinch-off voltage. In addition, a gate structure of the conventional D-mode FETs such as depletion mode metal-insulator-semiconductor field effect transistors (D-mode MISFETs) requires forming a gate recess. However, the etching depth of the gate recess is not easy to be precisely controlled, which leads to instability of the threshold voltage (Vt) of the D-mode MISFETs. In addition, interface traps are usually produced between the gate dielectric layer and the semiconductor layer of the D-mode MISFETs, thereby reducing the reliability of the D-mode MISFETs. SUMMARY OF THE INVENTION In view of this, the present disclosure provides a high electron mobility transistor (HEMT) structure and a fabrication method thereof. The HEMT structure integrates an enhancement-mode (E-mode) HEMT and a depletion-mode (D-mode) HEMT, and the fabrication method thereof does not require additional process steps. A layout of a compound semiconductor cap layer of the HEMT structure is used to achieve the effect of lateral depletion, so that the HEMT structures of the present disclosure provide a start-up function. Moreover, through adjusting the width of a gap between segments of the compound semiconductor cap layer, the threshold voltage (Vt) of the D-mode HEMT is precisely controlled, so that the HEMT structures of the present disclosure have stable and precise electrical characteristics. According to one embodiment of the present disclosure, a high electron mobility transistor structure is provided and includes a substrate, a compound semiconductor channel layer, a compound semiconductor barrier layer, a compound semiconductor cap layer, a gate electrode, a source electrode and a drain electrode. The compound semiconductor channel layer is disposed on the substrate. The compound semiconductor barrier layer is disposed on the compound semiconductor channel layer. The compound semiconductor cap layer is disposed on the compound semiconductor barrier layer. Moreover, the compound semiconductor cap layer includes a first segment and a second segment arranged along a first direction, and there is a first gap between the first segment and the second segment. The gate electrode is disposed on the compound semiconductor cap layer. The source electrode and the drain electrode are disposed on the compound semiconductor barrier layer, arranged along a second direction, and respectively located on two opposite sides of the compound semiconductor cap layer. According to one embodiment of the present disclosure, a fabrication method of a high electron mobility transistor structure is provided and includes the following steps. A compound semiconductor channel layer is formed on a substrate. A compound semiconductor barrier layer is formed on the compound semiconductor channel layer. A compound semiconductor cap layer is formed on the compound semiconductor barrier layer. The compound semiconductor cap layer includes a first segment and a second segment arranged along a first direction, and there is a first gap between the first segment and the second segment. A gate electrode is formed on the compound semiconductor cap layer. In addition, a source electrode and a drain electrode are formed on the compound semiconductor barrier layer. The source electrode and the drain electrode are arranged along a second direction, and respectively located on two opposite sides of the compound semiconductor cap layer. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced f