US-20260129900-A1 - SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

US20260129900A1US 20260129900 A1US20260129900 A1US 20260129900A1US-20260129900-A1

Abstract

A method includes forming a gate stack for a short-channel device and a longer-channel device; forming a first metal cap layer over the gate stacks for the short-channel device and the longer-channel device, wherein the first metal cap layer of the longer-channel device has a metal-cap recess; forming a first dielectric cap layer in the metal-cap recess; selectively removing in parallel, a portion of the gate stacks and first metal cap layer for the short-channel device and the longer-channel device; forming a first channel recess between spacers in the short-channel device and a second channel recess between a spacer and the first dielectric cap layer in the longer-channel device by the selectively removing; wherein each of the first channel recess and the second channel recess has a width dimension and a difference between the width dimensions of the first channel recess and second channel recess is less than 3 nm.

Inventors

Shih-Chieh Chao
Ryan Chia-Jen Chen
Yih-Ann Lin
Yu-Hsien Lin
Li-Wei Yin
Tzu-Wen Pan
Jih-Sheng Yang

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20251229

Claims (20)

1 . A semiconductor device comprising, comprising: a short-channel device having a gate stack and a first channel length; a longer-channel device having a gate stack and a second channel length that is greater than the first channel length; a first metal cap layer over the gate stack for the short-channel device and the gate stack for the longer-channel device, wherein the first metal cap layer of the longer-channel device has a metal-cap recess in the first metal cap layer; a first dielectric cap layer in the metal-cap recess in the longer-channel device; a first channel recess between spacers in the short-channel device; a second channel recess between a spacer and the first dielectric cap layer in the longer-channel device; wherein each of the first channel recess and the second channel recess has a gap dimension from a top of the recess to a bottom of the recess and wherein a ratio of a difference between the gap dimensions of the first channel recess and second channel recess is within a range of approximately 0.4 to approximately 2.8; a second metal cap layer over the gate stack and first metal cap layer for the short-channel device and the gate stack and first metal cap layer for the longer-channel device; a second dielectric cap layer over the second metal cap layer over the short-channel device and over the second metal cap layer over the longer-channel device.
2 . The semiconductor device of claim 1 , wherein the first channel length is approximately 25 nanometers (nm) or less, and the second channel length is approximately 30 nm to approximately 60 nm.
3 . The semiconductor device of claim 1 , wherein the first channel length is approximately 25 nanometers (nm) or less, and the second channel length is approximately 80 nm to approximately 200 nm.
4 . The semiconductor device of claim 1 , wherein a difference between the gap dimensions of the first channel recess and second channel recess is within plus or minus approximately 2 nm to approximately 5 nm.
5 . The semiconductor device of claim 1 , wherein each of the first channel recess and the second channel recess has a width dimension and a difference between the width dimensions of the first channel recess and second channel recess is less than 3 nm.
6 . The semiconductor device of claim 5 , wherein the width dimension of the first channel recess is approximately 10 nm to approximately 15 nm and the width dimension of the second channel recess is approximately 7 nm to approximately 18 nm.
7 . The semiconductor device of claim 6 , wherein the first dielectric cap layer has a width of approximately 15 nm to approximately 30 nm.
8 . The semiconductor device of claim 6 , wherein the first dielectric cap layer has a width of approximately 40 nm to approximately 180 nm.
9 . The semiconductor device of claim 1 , wherein the gap dimension of the first channel recess is approximately 30 nm to approximately 70 nm and the gap dimension of the second channel recess is approximately 25 nm to approximately 75 nm.
10 . A semiconductor device, comprising: a short-channel device having a gate stack and a first channel length; a mid-channel device having a gate stack and a second channel length greater than the first channel length; a longer-channel device having a gate stack and a third channel length greater than the second channel length; a first metal cap layer over the gate stack for the short-channel device, the gate stack for the mid-channel device, and the gate stack for the longer-channel device; a first metal-cap recess in the first metal cap layer of the mid-channel device and a first dielectric cap layer in the first metal-cap recess; a second metal-cap recess in the first metal cap layer of the longer-channel device and a second dielectric cap layer in the second metal-cap recess; a first channel recess between spacers in the short-channel device, a second channel recess between a spacer and the first dielectric cap layer in the mid-channel device, and a third channel recess between a spacer and the second dielectric cap layer in the longer-channel device; wherein each of the first channel recess, the second channel recess, and the third channel recess has a gap dimension from a top of the recess to a bottom of the recess; wherein a ratio of a difference between the gap dimensions of the first channel recess and the second channel recess is within a range of approximately 0.4 to approximately 2.8, and a ratio of a difference between the gap dimensions of the first channel recess and the third channel recess is within a range of approximately 0.4 to approximately 2.8; a second metal cap layer over the gate stack and first metal cap layer for the short-channel device, the gate stack and first metal cap layer for the mid-channel device, and the gate stack and first metal cap layer for the longer-channel device; and a second dielectric cap layer over the second metal cap layer over the short-channel device, the second metal cap layer over the mid-channel device, and the second metal cap layer over the longer-channel device.
11 . The semiconductor device of claim 10 , wherein: each of the first channel recess, the second channel recess, and the third channel recess has a width dimension; a difference between the width dimensions of the first channel recess and second channel recess is less than 3 nanometers (nm); and a difference between the width dimensions of the first channel recess and third channel recess is less than 3 nm.
12 . The semiconductor device of claim 10 , wherein: a difference between the gap dimensions of the first channel recess and the second channel recess is within plus or minus approximately 2 nm to approximately 5 nm; and a difference between the gap dimensions of the first channel recess and the third channel recess is within plus or minus approximately 2 nm to approximately 5 nm.
13 . The semiconductor device of claim 10 wherein the ratio of the difference between the gap dimensions of the first channel recess and the second channel recess is within a range of approximately 0.73 to approximately 1.71, and the ratio of the difference between the gap dimensions of the first channel recess and the third channel recess is within a range of approximately 0.73 to approximately 1.71.
14 . A semiconductor device comprising: a short-channel device having a gate stack and a channel length less than a first threshold length; a longer-channel device having a gate stack and channel length greater than a second threshold length that is greater than the first threshold length; a first metal cap layer over the gate stack for the short-channel device and the gate stack for the longer-channel device, wherein the first metal cap layer of the longer-channel device has a metal-cap recess in the first metal cap layer; a first dielectric cap layer in the metal-cap recess in the longer-channel device; a first channel recess between spacers in the short-channel device, and a second channel recess between a spacer and the first dielectric cap layer in the longer-channel device; wherein each of the first channel recess and the second channel recess has a width dimension and a difference between the width dimensions of the first channel recess and the second channel recess is less than 3 nanometers (nm); a second metal cap layer over the gate stack and first metal cap layer for the short-channel device and the gate stack and first metal cap layer for the longer-channel device; and a second dielectric cap layer over the second metal cap layer in the first channel recess of the short-channel device and the second metal cap layer in the second channel recess of the longer-channel device.
15 . The semiconductor device of claim 14 , wherein the short-channel device has a channel length of approximately 25 nm or less and the longer-channel device comprises a mid-channel device having a channel length of approximately 30 nm to approximately 60 nm.
16 . The semiconductor device of claim 14 , wherein the short-channel device has a channel length of approximately 25 nm or less and the longer-channel device comprises a long-channel device having a channel length of approximately 80 nm to approximately 200 nm.
17 . The semiconductor device of claim 14 , wherein the width dimension of the first channel recess is approximately 10 nm to approximately 15 nm and the width dimension of the second channel recess is approximately 7 nm to approximately 18 nm.
18 . The semiconductor device of claim 17 , wherein the first dielectric cap layer has a width of approximately 15 nm to approximately 30 nm.
19 . The semiconductor device of claim 17 , wherein the first dielectric cap layer has a width of approximately 40 nm to approximately 180 nm.
20 . The semiconductor device of claim 14 , wherein a bottom edge of first dielectric cap layer extends below portions of the first metal cap layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit as a divisional of U.S. patent application Ser. No. 18/192,146, filed Mar. 29, 2023. U.S. patent application Ser. No. 18/192,146 is incorporated herein by reference. BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum feature sizes are reduced, additional problems arise that should be addressed. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A a perspective view of a semiconductor device, in accordance with some embodiments. FIG. 1B illustrates a cross-sectional view of FIG. 1A along cutline X-X′, in accordance with some embodiments. FIG. 2 is a process flow chart depicting an example fabrication process for forming, in a semiconductor device, metal gates that include a gate stack, a metal cap disposed above the gate stack, and a dielectric layer (such as silicon nitride (SiN)) disposed above the metal cap, in accordance with some embodiments. FIGS. 3A-3Q are diagrams depicting enlarged views of an example area at various stages of fabricating a semiconductor device, in accordance with some embodiments. FIG. 4 is a process flow chart depicting an example method of semiconductor fabrication that includes metal drain (MD) fabrication and via gate (VG) fabrication after metal gate formation, in accordance with some embodiments, in accordance with some embodiments. FIGS. 5A-5E are diagrams depicting expanded views of an example area at various stages of semiconductor fabricating including metal drain fabrication and via gate fabrication, in accordance with some embodiments. FIG. 6 is a process flow chart depicting an example method of semiconductor fabrication, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For the sake of brevity, conventional techniques related to conventional semiconductor device fabrication may not be described in detail herein. Moreover, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. In particular, various processes in the fabrication of semiconductor devices are well-known and so, in the interest of brevity, many conventional processes will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. As will be readily apparent to those skilled in the art upon a complete reading of the disclosure, the structures disclosed herein may be employed with a variety of technologies, and may be incorporated into a variety of semiconductor devices and products. Further, it is noted that semiconductor device structures include a varying number of components and that single components shown in the illustrations may be representative of multiple components. Furthermore, spatially relative terms, such as “over”, “overlying”, “above”, “upper”, “top”, “under”, “underlying”, “below”, “lower”, “bottom”, and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. When a spatially relative term, such as those listed above, is used to describe a first element with respect to a second element, the