US-20260129901-A1 - SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Abstract

A semiconductor device includes: a substrate; a channel layer having a fin shape and protruding from the substrate in a first direction perpendicular to an upper surface of the substrate; an external gate electrode on a first side surface of the channel layer, a second side surface of the channel layer that is opposite to the first side surface, and an upper surface of the channel layer; and an internal gate electrode contacting a lower surface of the channel layer, wherein the internal gate electrode includes a material that is different from a material from of the external gate electrode.

Inventors

• DEOKHWAN KIM
• Sungmin Kim
• JaeMyeong Kim
• Jeonggeol KIM
• Yongkyung LEE

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20250801

Priority Date

20241107

Claims (20)

1. 1 . A semiconductor device comprising: a substrate; a channel layer having a fin shape and protruding from the substrate in a first direction perpendicular to an upper surface of the substrate; an external gate electrode on a first side surface of the channel layer, a second side surface of the channel layer that is opposite to the first side surface, and an upper surface of the channel layer; and an internal gate electrode contacting a lower surface of the channel layer, wherein the internal gate electrode comprises a material that is different from a material from of the external gate electrode.
2. 2 . The semiconductor device of claim 1 , wherein the material of the internal gate electrode has etch selectivity with respect to the external gate electrode.
3. 3 . The semiconductor device of claim 1 , wherein the material of the internal gate electrode and the material of the external gate electrode comprise at least one of metal, metal nitride, metal oxide, and doped polysilicon.
4. 4 . The semiconductor device of claim 1 , wherein the external gate electrode comprises a first conductive layer on the channel layer and a second conductive layer on the first conductive layer.
5. 5 . The semiconductor device of claim 1 , wherein the channel layer comprises a Group IV semiconductor, a Group III-V semiconductor compound, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional semiconductor, quantum dots, or an organic semiconductor.
6. 6 . The semiconductor device of claim 1 , wherein the internal gate electrode comprises: an internal conductive layer comprising a material that is different from the material of the external gate electrode; and a barrier layer on an upper surface of the internal conductive layer and a lower surface of the internal conductive layer.
7. 7 . A semiconductor device comprising: a substrate; a first unit device on the substrate; and a second unit device on the substrate and spaced apart from the first unit device, wherein each of the first unit device and the second unit device comprises: a channel layer having a fin shape and protruding from the substrate in a first direction perpendicular to an upper surface of the substrate; an external gate electrode on a first side surface of the channel layer, a second side surface of the channel layer that is opposite to the first side surface, and an upper surface of the channel layer; and an internal gate electrode contacting a lower surface of the channel layer, and wherein the internal gate electrode comprises a material that is a different from a material from of the external gate electrode.
8. 8 . The semiconductor device of claim 7 , wherein the material of the internal gate electrode of each of the first unit device and the second unit device has etch selectivity with respect to the external gate electrode.
9. 9 . The semiconductor device of claim 7 , wherein, in a second direction that is perpendicular to the first direction, a thickness of the external gate electrode of the first unit device is different from a thickness of the external gate electrode of the second unit device.
10. 10 . The semiconductor device of claim 7 , wherein the external gate electrode of each of the first unit device and the second unit device comprises a first conductive layer on the channel layer and a second conductive layer on the first conductive layer.
11. 11 . The semiconductor device of claim 10 , wherein, in a second direction that is perpendicular to the first direction, a thickness of the first conductive layer of the first unit device is different from a thickness of the first conductive layer of the second unit device.
12. 12 . The semiconductor device of claim 7 , wherein the material of the internal gate electrode and the material of the external gate electrode of each of the first unit device and the second unit device comprise at least one of metal, metal nitride, metal oxide, and doped polysilicon.
13. 13 . The semiconductor device of claim 7 , wherein the channel layer of each of the first unit device and the second unit device comprises a Group IV semiconductor, a Group III-V semiconductor compound, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional semiconductor, quantum dots, or an organic semiconductor.
14. 14 . The semiconductor device of claim 7 , wherein the internal gate electrode of each of the first unit device and the second unit device comprises: an internal conductive layer comprising a material that is different from the material of the external gate electrode; and a barrier layer on an upper surface of the internal conductive layer and a lower surface of the internal conductive layer.
15. 15 . A method of fabricating a semiconductor device, the method comprising: forming a first channel layer and a second channel layer on a substrate that extend in a first direction perpendicular to an upper surface of the substrate; forming a first through-hole in a lower of the first channel layer and a second through-hole in a lower portion of the second channel layer; forming a first internal gate electrode filling the first through-hole and a second internal gate electrode filling and the second through-hole; forming a first external gate material layer on the substrate, the first external gate material layer covering the first channel layer, the first internal gate electrode, the second channel layer and the second internal gate electrode; selectively etching and removing the first external gate material layer in areas in which the first external gate material layer covers the first channel layer and the first internal gate electrode; forming a second external gate material layer on the first external gate material layer covering the first channel layer, the first internal gate electrode, the second channel layer, and the second internal gate electrode; forming a first external gate electrode on the first channel layer and the first internal gate electrode; and forming a second external gate electrode on the second channel layer and the second internal gate electrode, wherein the first internal gate electrode comprises a material that is different from a material of the first external gate electrode, and the second internal gate electrode comprises a material that is different from a materials of the second external gate electrode.
16. 16 . The method of claim 15 , wherein a thickness of the second external gate electrode is different from a thickness of the first external gate electrode.
17. 17 . The method of claim 15 , wherein the first through-hole and the second through-hole are formed in a second direction that is perpendicular to the first direction.
18. 18 . The method of claim 15 , wherein the forming the first internal gate electrode and the second internal gate electrode comprises: forming an internal gate material layer in each of the first channel layer and the second channel layer to fill the first through-hole and the second through-hole; and etching and removing the internal gate material layer such that the internal gate material layer remains only in the first through-hole and the second through-hole.
19. 19 . The method of claim 18 , wherein the internal gate material layer comprises a material having etch selectivity with respect to the first external gate material layer.
20. 20 . The method of claim 15 , wherein the first internal gate electrode comprises a first internal conductive layer comprising a material that is different from the material of the first external gate electrode and a barrier layer on an upper surface of the first internal conductive layer and a lower surface of the first internal conductive layer, and wherein the second internal gate electrode comprises a second internal conductive layer comprising a material that is different from the material of the second external gate electrode and a barrier layer on an upper surface of the second internal conductive layer and a lower surface of the second internal conductive layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority to Korean Patent Application No. 10-2024-0156884, filed on Nov. 7, 2024, In the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND 1. Field The disclosure relates to a semiconductor device and a method of fabricating the same. 2. Description of Related Art In semiconductor devices such as fin field effect transistors (FinFET), a channel may be formed in a fin shape perpendicularly protruding from a substrate, and a gate electrode may surround three sides of the channel. Semiconductor devices having such a three-dimensional shape may exhibit high performance and implement a high integration density. Information disclosed in this Background section has already been known to or derived by the inventors before or during the process of achieving the embodiments of the present application, or is technical information acquired in the process of achieving the embodiments. Therefore, it may contain information that does not form the prior art that is already known to the public. SUMMARY Provided are a semiconductor device and a method of fabricating the same. Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure. According to an aspect of the disclosure, a semiconductor device includes: a substrate; a channel layer having a fin shape and protruding from the substrate in a first direction perpendicular to an upper surface of the substrate; an external gate electrode on a first side surface of the channel layer, a second side surface of the channel layer that is opposite to the first side surface, and an upper surface of the channel layer; and an internal gate electrode contacting a lower surface of the channel layer, wherein the internal gate electrode includes a material that is different from a material from of the external gate electrode. The material of the internal gate electrode may have etch selectivity with respect to the external gate electrode. The material of the internal gate electrode and the material of the external gate electrode may include at least one of metal, metal nitride, metal oxide, and doped polysilicon. The external gate electrode may include a first conductive layer on the channel layer and a second conductive layer on the first conductive layer. The channel layer may include a Group IV semiconductor, a Group III-V semiconductor compound, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional semiconductor, quantum dots, or an organic semiconductor. The internal gate electrode may include: an internal conductive layer including a material that is different from the material of the external gate electrode; and a barrier layer on an upper surface of the internal conductive layer and a lower surface of the internal conductive layer. According to an aspect of the disclosure, a semiconductor device includes: a substrate; a first unit device on the substrate; and a second unit device on the substrate and spaced apart from the first unit device, wherein each of the first unit device and the second unit device may include: a channel layer having a fin shape and protruding from the substrate in a first direction perpendicular to an upper surface of the substrate; an external gate electrode on a first side surface of the channel layer, a second side surface of the channel layer that is opposite to the first side surface, and an upper surface of the channel layer; and an internal gate electrode contacting a lower surface of the channel layer, and wherein the internal gate electrode includes a material that is a different from a material from of the external gate electrode. The material of the internal gate electrode of each of the first unit device and the second unit device may have etch selectivity with respect to the external gate electrode. In a second direction that is perpendicular to the first direction, a thickness of the external gate electrode of the first unit device is different from a thickness of the external gate electrode of the second unit device. The external gate electrode of each of the first unit device and the second unit device may include a first conductive layer on the channel layer and a second conductive layer on the first conductive layer. In a second direction that is perpendicular to the first direction, a thickness of the first conductive layer of the first unit device is different from a thickness of the first conductive layer of the second unit device. The material of the internal gate electrode and the material of the external gate electrode of each of the first unit device and the second unit device may include at least one of metal, metal nitride, metal oxide, and doped polysilicon. The channel layer of each of the