US-20260129902-A1 - ISOLATION STRUCTURE FOR ISOLATING EPITAXIALLY GROWN SOURCE/DRAIN REGIONS AND METHOD OF FABRICATION THEREOF

Abstract

A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.

Inventors

• Ta-Chun Lin
• Chun-Jun Lin
• Jhon Jhy Liaw
• Kuo-Hua Pan
• Kuan-Lin Yeh
• Mu-Chi Chiang

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20260105

Claims (20)

1. 1 . A semiconductor device, comprising: an active region; a source/drain structure disposed over the active region in a vertical direction in a cross-sectional side view, wherein the source/drain structure includes a first outermost lateral portion facing a first lateral direction and a second outermost lateral portion facing a second lateral direction in the cross-sectional side view; an isolation structure disposed directly adjacent to one of the first outermost lateral portion or the second outermost lateral portion; and a conductive contact comprising: a first portion positioned underlying and vertically aligned with the first outermost lateral portion; and a second portion positioned underlying and vertically aligned with the second outermost lateral portion.
2. 2 . The semiconductor device of claim 1 , wherein the conductive contact surrounds the source/drain structure, and a dimension of the conductive contact in the vertical direction exceeds a maximum dimension of the source/drain structure in the vertical direction.
3. 3 . The semiconductor device of claim 1 , wherein the conductive contact is in physical contact with the first outermost lateral portion and the second outermost lateral portion.
4. 4 . The semiconductor device of claim 1 , wherein: the source/drain structure comprises a first source/drain region and a second source/drain region that are laterally merged together; and a portion of the conductive contact is disposed between the first source/drain region and the second source/drain region.
5. 5 . The semiconductor device of claim 4 , wherein: the first source/drain region includes a first surface and a second surface disposed below the first surface; the second source/drain region includes a third surface and a fourth surface disposed below the third surface; and the portion of the conductive contact is in physical contact with the first surface of the first source/drain region and the third surface of the second source/drain region.
6. 6 . The semiconductor device of claim 1 , wherein the second outermost lateral portion is pointier than the first outermost lateral portion.
7. 7 . The semiconductor device of claim 6 , wherein the isolation structure is disposed directly adjacent to the first outermost lateral portion.
8. 8 . The semiconductor device of claim 7 , wherein the isolation structure forms an interface with the first outermost lateral portion.
9. 9 . The semiconductor device of claim 8 , wherein the interface is substantially linear and extends substantially in the vertical direction.
10. 10 . The semiconductor device of claim 1 , comprising a further source/drain structure disposed over the active region in the vertical direction in the cross-sectional side view, wherein: the isolation structure is disposed between the source/drain structure and the further source/drain structure; the further source/drain structure includes a third outermost lateral portion facing the first lateral direction and a fourth outermost lateral portion facing the second lateral direction in the cross-sectional side view; and the third outermost lateral portion and the fourth outermost lateral portion have different shapes in the cross-sectional side view.
11. 11 . The semiconductor device of claim 10 , wherein in the cross-sectional side view: the first outermost lateral portion and the third outermost lateral portion have similar shapes; and the second outermost lateral portion and the fourth outermost lateral portion have similar shapes.
12. 12 . The semiconductor device of claim 10 , comprising an additional source/drain structure disposed over the active region in the vertical direction in the cross-sectional side view, wherein the additional source/drain structure has a substantially smaller dimension than the source/drain structure or the further source/drain structure in the cross-sectional side view.
13. 13 . The semiconductor device of claim 1 , comprising a dielectric spacer layer disposed on surfaces of a lower portion, but not an upper portion, of the source/drain structure.
14. 14 . A semiconductor device, comprising: an active region; a source/drain structure disposed over the active region in a vertical direction in a cross-sectional side view, wherein the source/drain structure includes a first lateral protrusion protruding in a first lateral direction and a second lateral protrusion protruding in a second lateral direction in the cross-sectional side view; an isolation structure that forms an interface with the first lateral protrusion in the cross-sectional side view; and a source/drain contact that extends to a side surface of the isolation structure and at least the second lateral protrusion of the source/drain structure, wherein a portion of the isolation structure that is below the interface is separated from a portion of the source/drain structure by the source/drain contact in the first lateral direction.
15. 15 . The semiconductor device of claim 14 , wherein the source/drain contact extends to surfaces of the source/drain structure above and below the first lateral protrusion in the cross-sectional side view.
16. 16 . The semiconductor device of claim 14 , wherein: the source/drain structure includes a first epitaxial component and a second epitaxial component that are laterally merged together; and a portion of the source/drain contact is trapped underneath and between the first epitaxial component and the second epitaxial component.
17. 17 . The semiconductor device of claim 16 , comprising a spacer layer disposed between the portion of the source/drain contact and the first epitaxial component and the second epitaxial component.
18. 18 . A semiconductor device, comprising: an active region; a first source/drain structure disposed over the active region in a vertical direction in a cross-sectional side view; a second source/drain structure disposed over the active region in the vertical direction in the cross-sectional side view; an isolation structure disposed between the first source/drain structure and the second source/drain structure in the cross-sectional side view, wherein: the isolation structure defines a first substantially linear interface with the first source/drain structure and a second substantially linear interface with the second source/drain structure in the cross-sectional side view; and the first substantially linear interface extends from a topmost point where the isolation structure contacts the first source/drain structure to a bottommost point where the isolation structure contacts the first source/drain structure; and a first source/drain contact portion that is positioned underlying and vertically aligned with the first substantially linear interface.
19. 19 . The semiconductor device of claim 18 , comprising: a first source/drain contact that surrounds the first source/drain structure; and a second source/drain contact that surrounds the second source/drain structure, wherein: a portion of the first source/drain contact is disposed below and between two different segments of the first source/drain structure; and a portion of the second source/drain contact is disposed below and between two different segments of the second source/drain structure.
20. 20 . The semiconductor device of claim 19 , comprising a gate spacer material that is disposed between the portion of the first source/drain contact and the first source/drain structure and between the portion of the second source/drain contact and the second source/drain structure.

Description

RELATED APPLICATIONS The present application is a continuation of U.S. patent application Ser. No. 18/669,059 filed on May 20, 2024 and titled “Isolation Structure For Isolating Epitaxially Grown Source/Drain Regions And Method Of Fabrication Thereof”, which is a continuation of U.S. patent application Ser. No. 17/826,816 filed on May 27, 2022 and titled “Isolation Structure For Isolating Epitaxially Grown Source/Drain Regions And Method Of Fabrication Thereof”, issued on May 21, 2024 as U.S. Pat. No. 11,990,525, which is a continuation application of U.S. patent application Ser. No. 17/033,031 filed on Sep. 25, 2020 and titled “Isolation Structure for Isolating Epitaxially Grown Source/Drain Regions And Method Of Fabrication Thereof”, issued on May 31, 2022 as U.S. Pat. No. 11,349,002, the disclosures of each which are hereby incorporated by reference in their entireties. The present application is also related to U.S. patent application Ser. No. 16/917,778, filed on Jun. 30, 2020, entitled “Isolation Structure For Preventing Unintentional Merging of Epitaxially Grown Source/Drain”, the disclosure of which is hereby incorporated by reference in its entirety. BACKGROUND The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs. For example, as semiconductor devices continue to get scaled down, the space between adjacent transistors becomes smaller and smaller. The small spacing may cause the epitaxial source/drain features between adjacent transistors to merge into one another, which leads to electrical shorting between the adjacent transistors. Electrical shorting is undesirable because it may degrade device performance or even cause device failures. Therefore, although conventional methods of fabricating semiconductor devices have generally been adequate, they have not been satisfactory in all aspects. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A is a perspective view of an IC device in the form of a FinFET according to various aspects of the present disclosure. FIG. 1B is a planar top view of an IC device in the form of a FinFET according to various aspects of the present disclosure. FIG. 1C is a perspective view of an IC device in the form of a GAA device according to various aspects of the present disclosure. FIGS. 2A-12A and 2B-12B are cross-sectional side views of various embodiments of IC devices at various stages of fabrication according to various aspects of the present disclosure. FIG. 13 is a circuit schematic of an SRAM cell according to various aspects of the present disclosure. FIG. 14 is a block diagram of a manufacturing system according to various aspects of the present disclosure. FIG. 15 is a flowchart illustrating a method of fabricating a semiconductor device according to various aspects of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplici