US-20260129904-A1 - SEMICONDUCTOR DEVICE

Abstract

A semiconductor device, including: a semiconductor substrate having a termination structure portion surrounding an active region in a plan view; a first semiconductor layer provided in the semiconductor substrate; a second semiconductor layer provided on the first semiconductor layer; a first parallel pn structure, in which first and second column regions are disposed repeatedly alternating with each other, provided in the second semiconductor layer and in the active region; a plurality of first semiconductor regions in the first parallel pn structure; a plurality of second semiconductor regions selectively provided in the first semiconductor regions; a plurality of gate electrodes provided respectively via gate insulating films; and a second parallel pn structure, in which third and fourth column regions are disposed repeatedly alternating with each other, provided in the second semiconductor layer and in the termination structure portion. The second parallel pn structure is longer than the first parallel pn structure.

Inventors

• Shuhei TATEMICHI

Assignees

• FUJI ELECTRIC CO., LTD.

Dates

Publication Date

20260507

Application Date

20250930

Priority Date

20241106

Claims (7)

1. 1 . A semiconductor device, comprising: a semiconductor substrate of a first conductivity type, the semiconductor substrate having an active region, and a termination structure portion disposed outside the active region so as to surround a periphery of the active region in a plan view of the semiconductor device; a first semiconductor layer of the first conductivity type, provided in the semiconductor substrate at a main surface thereof, the first semiconductor layer having a dopant concentration lower than a dopant concentration of the semiconductor substrate; a second semiconductor layer of the first conductivity type, provided in the semiconductor substrate on the first semiconductor layer, the second semiconductor layer having a dopant concentration lower than the dopant concentration of the first semiconductor layer; a first parallel pn structure in which a plurality of first column regions of the first conductivity type and a plurality of second column regions of a second conductivity type are disposed repeatedly alternating with each other in a first direction parallel to the main surface, the first parallel pn structure being provided in the second semiconductor layer and in the active region; a plurality of first semiconductor regions of the second conductivity type, provided in the first parallel pn structure at a surface thereof, in the active region; a plurality of second semiconductor regions of the first conductivity type, selectively provided in the plurality of first semiconductor regions, at surfaces thereof, in the active region; a plurality of gate electrodes provided respectively via a plurality of gate insulating films, each of the plurality of gate insulating films being in contact with at least one of the plurality of first semiconductor regions and at least one of the plurality of second semiconductor regions; and a second parallel pn structure in which a plurality of third column regions of the first conductivity type and a plurality of fourth column regions of the second conductivity type are disposed repeatedly alternating with each other in the first direction, the second parallel pn structure being provided in the second semiconductor layer and in the termination structure portion, wherein in a second direction perpendicular to the main surface, a length of the second parallel pn structure is longer than a length of the first parallel pn structure.
2. 2 . The semiconductor device according to claim 1 , wherein in the second direction, an end of the second parallel pn structure is closer to the semiconductor substrate than is an end of the first parallel pn structure.
3. 3 . The semiconductor device according to claim 1 , wherein each of a dopant concentration of the plurality of first column regions and a dopant concentration of the plurality of third column regions is lower than the dopant concentration of the first semiconductor layer.
4. 4 . The semiconductor device according to claim 1 , wherein each of a dopant concentration of the plurality of first column regions and a dopant concentration of the plurality of third column regions is higher than the dopant concentration of the first semiconductor layer.
5. 5 . The semiconductor device according to claim 1 , wherein the first semiconductor layer includes: a first first-semiconductor-layer provided at the main surface of the semiconductor substrate, and a second first-semiconductor-layer provided on the first first-semiconductor-layer, a dopant concentration of the first first-semiconductor-layer is lower than the dopant concentration of the semiconductor substrate and higher than each of a dopant concentration of the plurality of first column regions and a dopant concentration of the plurality of third column regions, and a dopant concentration of the second first-semiconductor-layer is lower than each of the dopant concentration of the semiconductor substrate, the dopant concentration of the plurality of first column regions, and the dopant concentration of the plurality of third column regions.
6. 6 . The semiconductor device according to claim 1 , wherein one of the plurality of fourth column regions is provided at a border between the active region and the termination structure portion.
7. 7 . The semiconductor device according to claim 1 , wherein each of the plurality of third column regions and each of the plurality of fourth column regions has a first surface and a second surface opposite each other, the first surfaces not being exposed and the second surfaces facing the second semiconductor layer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2024-194643, filed on November 6, 2024, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention Embodiments of the disclosure relate to a semiconductor device. 2. Description of the Related Art One conventionally known superjunction semiconductor device achieves high reliability and L load avalanche breakdown (breakdown tolerance) by making the thickness of a parallel pn layer of an active area thinner than the thickness of a pn layer of a voltage withstanding area and providing an n+ intermediate drain layer having a higher concentration than that of an n drift region between the parallel pn layer and an n+ drain layer (for example, refer to Japanese Patent No. 4843843). SUMMARY OF THE INVENTION According to an embodiment of the present disclosure, a semiconductor substrate of a first conductivity type, the semiconductor substrate having an active region, and a termination structure portion disposed outside the active region so as to surround a periphery of the active region in a plan view of the semiconductor device; a first semiconductor layer of the first conductivity type, provided in the semiconductor substrate at a main surface thereof, the first semiconductor layer having a dopant concentration lower than a dopant concentration of the semiconductor substrate; a second semiconductor layer of the first conductivity type, provided in the semiconductor substrate on the first semiconductor layer, the second semiconductor layer having a dopant concentration lower than the dopant concentration of the first semiconductor layer; a first parallel pn structure in which a plurality of first column regions of the first conductivity type and a plurality of second column regions of a second conductivity type are disposed repeatedly alternating with each other in a first direction parallel to the main surface, the first parallel pn structure being provided in the second semiconductor layer and in the active region; a plurality of first semiconductor regions of the second conductivity type, provided in the first parallel pn structure at a surface thereof, in the active region; a plurality of second semiconductor regions of the first conductivity type, selectively provided in the plurality of first semiconductor regions, at surfaces thereof, in the active region; a plurality of gate electrodes provided respectively via a plurality of gate insulating films, each of the plurality of gate insulating films being in contact with at least one of the plurality of first semiconductor regions and at least one of the plurality of second semiconductor regions; and a second parallel pn structure in which a plurality of third column regions of the first conductivity type and a plurality of fourth column regions of the second conductivity type are disposed repeatedly alternating with each other in the first direction, the second parallel pn structure being provided in the second semiconductor layer and in the termination structure portion. In a second direction perpendicular to the main surface, a length of the second parallel pn structure is longer than a length of the first parallel pn structure. Objects, features, and advantages of the present invention are specifically set forth in or will become apparent from the following detailed description of the invention when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view depicting a structure of a silicon carbide semiconductor device according to an embodiment, along cutting line X-X’ in FIG. 3. FIG. 2 is a cross-sectional view depicting the structure of the silicon carbide semiconductor device according to the embodiment, along cutting line Y-Y’ in FIG. 3. FIG. 3 is a top view depicting the structure of the silicon carbide semiconductor device according to the embodiment. FIG. 4 is a cross-sectional view depicting another structure of the silicon carbide semiconductor device according to the embodiment, along cutting line X-X’ in FIG. 3. FIG. 5 is a cross-sectional view depicting another structure of the silicon carbide semiconductor device according to the embodiment, along cutting line X-X’ in FIG. 3. FIG. 6 is a cross-sectional view along cutting line X-X’ in FIG. 7, depicting a structure of the conventional silicon carbide semiconductor device. FIG. 7 is a top view of the structure of the conventional silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE INVENTION First, problems associated with the conventional techniques above are discussed. In a conventional semiconductor device, a problem arises in that the breakdown voltage of an edge area is difficult to increase to be higher than the breakdown voltage of the active area. An outline of an embodiment of the present disclosure is de