US-20260129905-A1 - SEMICONDUCTOR DEVICE HAVING AN ETCHING STOPPER LAYER ON A FIRST INSULATION LAYER

US20260129905A1US 20260129905 A1US20260129905 A1US 20260129905A1US-20260129905-A1

Abstract

According to one embodiment, a semiconductor device includes a semiconductor layer including a source area, a drain area and a channel area, a first insulating layer, an etching stopper layer located immediately above the channel area and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode in contact with the source area, and a drain electrode in contact with the drain area.

Inventors

Hajime Watakabe
Masashi TSUBUKU
Kentaro Miura
Akihiro Hanada
Takaya TAMARU

Assignees

MAGNOLIA WHITE CORPORATION

Dates

Publication Date: 20260507
Application Date: 20251229
Priority Date: 20211004

Claims (7)

1 . A semiconductor device comprising: an insulating substrate; a semiconductor layer provided above the insulating substrate and comprising a source area, a drain area, and a channel area; a first layer which covers the insulating semiconductor layer; a second insulating layer provided on the first insulating layer and overlapping the channel area, the second insulating layer including aluminum; a third insulating layer provided on the second insulating layer and being thicker than the first insulating layer; a gate electrode provided on the third insulating layer; a fourth insulating layer which covers the first insulating layer, the second insulating layer, the third insulating layer and the gate electrode and is in contact with the first insulating layer immediately above the source area and immediately above the drain area; a source electrode which is in contact with the source area in a first contact hole penetrating the first insulating layer and the fourth insulating layer; and a drain electrode which is in contact with the drain area in a second contact hole penetrating the first insulating layer and the fourth insulating layer, wherein the second insulating layer is formed of a material different from the first insulating layer, the third insulating layer and the fourth insulating layer, a side surface of the second insulating layer and a side surface of the third insulating layer are located between the source electrode and the drain electrode, and the fourth insulating layer is in contact with the side surface of the second insulating layer and the side surface of the third insulating layer.
2 . The semiconductor device of claim 1 , wherein the side surface of the third insulating layer is located immediately above the side surface of the second insulating layer, and a side surface of the gate electrode is located immediately above the side surface of the third insulating layer.
3 . The semiconductor device of claim 1 , wherein the semiconductor layer is an oxide semiconductor layer, and an impurity concentration of each of the source area and the drain area is higher than an impurity concentration of the channel area.
4 . The semiconductor device of claim 1 , wherein a thickness of the first insulating layer is greater than or equal to 70 nm and less than or equal to 100 nm.
5 . The semiconductor device of claim 1 , wherein a thickness of the second insulating layer is greater than or equal to 10 nm.
6 . The semiconductor device of claim 1 , wherein a thickness of the third insulating layer is greater than or equal to 100 nm.
7 . The semiconductor device of claim 1 , wherein the third insulating layer is a single-layer body of silicon oxide, a single-layer body of silicon nitride or a stacked layer body of a silicon oxide layer and a silicon nitride layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. application Ser. No. 17/958,437, filled on Oct. 3, 2022, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-163342, filed Oct. 4, 2021, the entire contents of each are incorporated herein by reference. FIELD Embodiments described herein relate generally to a semiconductor device and a manufacturing method thereof. BACKGROUND In recent years, various semiconductor devices comprising a transistor using an oxide semiconductor have been suggested. For example, a technique of applying an oxide semiconductor having a stacked structure of an amorphous film and a crystallized film and providing an etching stopper layer immediately above a gate electrode has been known. In this type of transistor, for example, a high voltage of 30 V or higher could be applied to the gate electrode. The semiconductor device is required to obtain stable transistor characteristics even when high voltage is applied to the gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing an example of a semiconductor device 1 according to an embodiment. FIG. 2 is a diagram for explaining a manufacturing method of the semiconductor device 1. FIG. 3 is a diagram for explaining the manufacturing method of the semiconductor device 1. FIG. 4 is a diagram for explaining the manufacturing method of the semiconductor device 1. FIG. 5 is a cross-sectional view showing another example of the semiconductor device 1 according to the embodiment. DETAILED DESCRIPTION In general, according to one embodiment, a semiconductor device comprises an insulating substrate, a semiconductor layer provided above the insulating substrate, and comprising a source area, a drain area, and a channel area in which a resistance is higher than resistances of the source area and the drain area, a first insulating layer which covers the semiconductor layer, an etching stopper layer provided on the first insulating layer, located immediately above the channel area, and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode provided on the second insulating layer, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode which is in contact with the source area in a first contact hole penetrating the first insulating layer and the third insulating layer, and a drain electrode which is in contact with the drain area in a second contact hole penetrating the first insulating layer and the third insulating layer. According to another embodiment, a manufacturing method of a semiconductor device comprises forming a semiconductor layer, a first insulating layer, an etching stopper layer, a second insulating layer and a metal layer above an insulating substrate in series, forming a patterned resist on the metal layer, etching the metal layer using the resist to form a gate electrode, etching the second insulating layer using the resist to partly expose an upper surface of the etching stopper layer, etching the etching stopper layer to partly expose an upper surface of the first insulating layer, and implanting ions into the semiconductor layer via the first insulating layer using the gate electrode as a mask. Embodiments will be described hereinafter with reference to the accompanying drawings. The disclosure is merely an example, and proper changes in keeping with the spirit of the invention, which are easily conceivable by a person of ordinary skill in the art, come within the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the widths, thicknesses, shapes, etc., of the respective parts are illustrated schematically in the drawings, rather than as an accurate representation of what is implemented. However, such schematic illustration is merely exemplary, and in no way restricts the interpretation of the invention. In addition, in the specification and drawings, structural elements which function in the same or a similar manner to those described in connection with preceding drawings are denoted by like reference numbers, detailed description thereof being omitted unless necessary. The semiconductor device 1 of the present embodiment can be applied to various display devices such as a liquid crystal display device, an organic electroluminescent display device, an electrophoresis display device and an LED display device, various sensors such as a capacitive sensor and an optical sensor, and other electronic devices. FIG. 1 is a cross-sectional view showing an example of a semiconductor device 1 according to an embodiment. The semiconductor device 1 comprises an