US-20260129906-A1 - SEMICONDUCTOR DEVICES WITH MODIFIED SOURCE/DRAIN FEATURE AND METHODS THEREOF

Abstract

A semiconductor structure includes a channel region over a substrate, a gate structure engaging the channel region, a gate spacer disposed on sidewalls of the gate structure, a source/drain (S/D) feature abutting the channel region, an S/D contact landing on a top surface of the S/D feature, and a dielectric layer disposed on a sidewall of the gate spacer. The S/D feature includes a first layer and a second layer underneath the first layer. The second layer differs from the first layer in composition. The dielectric layer interfaces with both the first layer and the second layer of the S/D feature. In a cross-sectional view along a lengthwise direction of the channel region, a bottommost point of the top surface of the S/D feature is below a top surface of the channel region.

Inventors

• Wei-Jen Lai
• Wei-Yang Lee
• Ting-Wen Shih
• De-Gang Chen

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20260105

Claims (20)

1. 1 . A semiconductor structure, comprising: a channel region over a substrate; a gate structure engaging the channel region; a gate spacer disposed on sidewalls of the gate structure; a source/drain (S/D) feature abutting the channel region; an S/D contact landing on a top surface of the S/D feature; and a dielectric layer disposed on a sidewall of the gate spacer, wherein the S/D feature includes a first layer and a second layer underneath the first layer, the second layer differs from the first layer in composition, and the dielectric layer interfaces with both the first layer and the second layer of the S/D feature, wherein in a cross-sectional view along a lengthwise direction of the channel region, a bottommost point of the top surface of the S/D feature is below a top surface of the channel region.
2. 2 . The semiconductor structure of claim 1 , wherein in the cross-sectional view along the lengthwise direction of the channel region, a topmost point of the top surface of the S/D feature is above the top surface of the channel region.
3. 3 . The semiconductor structure of claim 2 , wherein the topmost point of the top surface of the S/D feature is above the top surface of the channel region for about 1 nm to about 5 nm.
4. 4 . The semiconductor structure of claim 1 , wherein a bottommost portion of the S/D contact is below the top surface of the channel region.
5. 5 . The semiconductor structure of claim 1 , wherein a middle portion of the top surface of the S/D feature protrudes upwardly into the S/D contact.
6. 6 . The semiconductor structure of claim 1 , wherein a middle portion of the top surface of the S/D feature has a concave shape.
7. 7 . The semiconductor structure of claim 1 , wherein the first layer contours a bottom surface of the S/D contact and the second layer is spaced apart from the bottom surface of the S/D contact.
8. 8 . The semiconductor structure of claim 1 , further comprising: inner spacers disposed between the S/D feature and the gate structure, wherein the first layer interfaces with the inner spacers, and the second layer is spaced apart from the inner spacers.
9. 9 . The semiconductor structure of claim 1 , wherein the dielectric layer includes a contact etch stop layer disposed on the S/D feature and an inter-layer dielectric layer disposed on the contact etch stop layer.
10. 10 . The semiconductor structure of claim 1 , wherein the second layer interfaces with a top surface of the substrate.
11. 11 . A semiconductor structure, comprising: a plurality of first nanostructures vertically stacked above a substrate; a first gate structure wrapping around at least one of the first nanostructures; a first gate spacer disposed on sidewalls of the first gate structure; a first epitaxial feature abutting the first nanostructures; a plurality of second nanostructures vertically stacked above the substrate; a second gate structure wrapping around at least one of the second nanostructures; a second gate spacer disposed on sidewalls of the second gate structure; and a second epitaxial feature abutting the second nanostructures, wherein in a cross-sectional view along a lengthwise direction of the first and second nanostructures, the first epitaxial feature is narrower and taller than the second epitaxial feature.
12. 12 . The semiconductor structure of claim 11 , wherein the first epitaxial feature includes a first epitaxial layer and a second epitaxial layer disposed on the first epitaxial layer, the first epitaxial layer and the second epitaxial layer include different dopant concentrations, and the second epitaxial layer partially covers a top surface of the first epitaxial layer.
13. 13 . The semiconductor structure of claim 12 , wherein the second epitaxial layer is spaced apart from the first gate spacer.
14. 14 . The semiconductor structure of claim 12 , wherein the second epitaxial feature includes a third epitaxial layer and a fourth epitaxial layer disposed on the third epitaxial layer, the third epitaxial layer and the fourth epitaxial layer include different dopant concentrations, and the fourth epitaxial layer covers a top surface of the third epitaxial layer.
15. 15 . The semiconductor structure of claim 14 , wherein the fourth epitaxial layer interfaces with the second gate spacer.
16. 16 . The semiconductor structure of claim 14 , wherein the fourth epitaxial layer is spaced apart from the second gate spacer.
17. 17 . A semiconductor structure, comprising: a first gate structure engaging a first channel region, the first gate structure including a first sidewall; a second gate structure engaging a second channel region, the second gate structure including a second sidewall opposing the first sidewall; a first gate spacer disposed on the first sidewall of the first gate structure; a second gate spacer disposed on the second sidewall of the second gate structure; a source/drain (S/D) feature sandwiched between the first and second channel regions; and a dielectric layer disposed on sidewalls of the first and second gate spacers, wherein the S/D feature includes a first epitaxial layer and a second epitaxial layer disposed on the first epitaxial layer, the first epitaxial layer includes a dopant concentration different from the second epitaxial layer, and the second epitaxial layer is free of contact with either of the first and second gate spacers, and the dielectric layer interfaces with both the first epitaxial layer and the second epitaxial layer.
18. 18 . The semiconductor structure of claim 17 , wherein a topmost portion of the S/D feature is above top surfaces of the first and second channel regions.
19. 19 . The semiconductor structure of claim 18 , wherein a middle point of a top surface of the S/D feature is below the top surfaces of the first and second channel regions.
20. 20 . The semiconductor structure of claim 17 , wherein a top surface of the S/D feature includes a convex shape with an edge point of the convex shape below top surfaces of the first and second channel regions.

Description

PRIORITY This application is a continuation of U.S. patent application Ser. No. 18/767,291, filed on Jul. 9, 2024, which is a divisional of U.S. patent application Ser. No. 17/464,500, filed on Sep. 1, 2021, now issued U.S. Pat. No. 12,080,800, which claims priority to U.S. Provisional Patent Application No. 63/157,255 filed on Mar. 5, 2021, each of which is incorporated herein by reference in its entirety. BACKGROUND The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed. Recently, multi-gate transistors have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate transistor that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure which extends from a substrate on which it is formed, and which is used to form the FET channel. A further type of multi-gate transistor, introduced in part to address performance challenges associated with some configurations of FinFETs, is the gate-all-around (GAA) transistor. The GAA device gets its name from the gate structure which extends completely around the channel region, providing access to the channel on four sides. The GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. In general, The GAA devices may be implemented, for example, in cases where FinFETs can no longer meet performance requirements. However, GAA device fabrication can be challenging, and current methods continue to face challenges with respect to both device fabrication and performance. For example, high parasitic capacitance may lead to lower device speed (e.g., RC delays) when separation distances between the active device regions are reduced to meet design requirements of smaller technology nodes. While methods of reducing parasitic capacitance in IC devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all aspects. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A, 1B and 1C illustrate flowcharts of a method for forming a semiconductor device including modified source/drain (S/D) features, according to one or more aspects of the present disclosure. FIG. 2A illustrates a three-dimensional perspective view of a portion of an example semiconductor device according to one or more aspects of the present disclosure. FIG. 2B illustrates a planar top view of the semiconductor device shown in FIG. 2A according to one or more aspects of the present disclosure. FIG. 3 illustrates a three-dimensional perspective view of the semiconductor device during an intermediate stage of the method shown in FIGS. 1A, 1B, and/or 1C according to one or more aspects of the present disclosure. FIGS. 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 12C, 12D, 13, 14, 15, 16, 17, 18A, 19A, 20A, 20C and 20D illustrate cross-sectional views of the semiconductor device taken along line AA′ as shown in FIGS. 2A and/or 2B during intermediate stages of the method shown in FIGS. 1A, 1B, and/or 1C according to one or more aspects of the present disclosure. FIGS. 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 18B, 19B, and 20B illustrate cross-sectional views of the semiconductor device taken along line BB′ as shown in FIGS. 2A and/or 2B during intermediate stages of the method shown in FIGS. 1A, 1B and/or 1C according to one or more aspects of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the prese