US-20260129907-A1 - CAPPED BACKSIDE CONTACTS

Abstract

A semiconductor integrated circuit device includes a backside contact in direct contact with a source/drain region and a backside contact cap in direct contact with the backside contact. The device further includes a backside spacer in direct contact with respective sidewalls of the backside contact and the backside contact cap. The device further includes a backside S/D region contact via in direct contact with the backside contact, in direct contact with the backside spacer, and in direct contact with the backside contact cap. The device may further include a backside gate region contact via. The backside contact cap may provide adequate electrical and structural protection of the backside contact which may enable a nearby placement of the backside gate region contact via. Consequently, wire/signal routing congestion issues may be reduced and functionality of an associated backside back end of line network may be enhanced.

Inventors

• Fabio Carta
• Ruilong Xie
• Tao Li
• QIANWEN CHEN
• Joshua Mark Rubin

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260507

Application Date

20241101

Claims (20)

1. 1 . A semiconductor integrated circuit (IC) device comprising: a backside contact in direct contact with a source/drain region; a backside contact cap in direct contact with the backside contact; a backside spacer in direct contact with respective sidewalls of the backside contact and the backside contact cap; and a backside S/D region contact via in direct contact with the backside contact, in direct contact with the backside spacer, and in direct contact with the backside contact cap.
2. 2 . The semiconductor IC device of claim 1 , further comprising: a plurality of channels direct connected to a S/D region; a gate directly connected to the plurality of channels; and a backside gate contact via in direct contact with the gate, in direct contact with the backside spacer, and in direct contact with the backside contact cap.
3. 3 . The semiconductor IC device of claim 2 , further comprising: A backside interlayer dielectric (ILD) in direct contact with the backside spacer, in direct contact with the backside S/D region contact via, and in direct contact with the backside gate contact via.
4. 4 . The semiconductor IC device of claim 3 , wherein the backside contact cap is composed of a first dielectric material, wherein the backside spacer is composed of a second dielectric material, wherein the backside ILD is composed of a third dielectric material, and wherein each of the first dielectric material, the second dielectric material, and the third dielectric material are relatively different dielectric materials.
5. 5 . The semiconductor IC device of claim 2 , further comprising: a gate spacer in direct contact with the gate; and a plurality of inner spacers, each inner spacer of the plurality of inner spacers in direct contact with at least one channel of the plurality of channels.
6. 6 . The semiconductor IC device of claim 5 , wherein the gate spacer, the plurality of inner spacers, and the backside spacer are vertically inline.
7. 7 . The semiconductor IC device of claim 2 , wherein a topmost surface of the backside contact is below a bottommost channel of the plurality of channels and a top surface of the backside spacer.
8. 8 . A semiconductor integrated circuit (IC) device comprising: a plurality of channels each directly connected to a first source/drain (S/D) region and directly connected to a second S/D region; a first backside contact in direct contact with the first S/D region; a second backside contact in direct contact with the second S/D region; a first backside contact cap in direct contact with the first backside contact; a second backside contact cap in direct contact with the second backside contact; a first backside spacers in direct contact with respective sidewalls of the first backside contact and the first backside contact cap; a second backside spacers in direct contact with respective sidewalls of the second backside contact and the second backside contact cap; and a backside gate contact via in direct contact with a gate, in direct contact with one of the first backside spacers, and in direct contact with one of the second backside spacers.
9. 9 . The semiconductor IC device of claim 8 , wherein the backside gate contact via is in direct contact with the first backside contact cap and in direct contact with the second backside contact cap.
10. 10 . The semiconductor IC device of claim 9 , further comprising: a frontside contact directly connected to a top surface of the second S/D region.
11. 11 . The semiconductor IC device of claim 10 , further comprising: a frontside contact via directly connected to the frontside contact, directly connected to the second backside contact, and directly connected to a sidewall of the second S/D region.
12. 12 . The semiconductor IC device of claim 11 , further comprising: a backside S/D contact via in direct contact with the first backside contact and in direct contact with the first backside spacers.
13. 13 . The semiconductor IC device of claim 12 , further comprising: a backside interlayer dielectric (ILD) in direct contact with the first backside spacers, in direct contact with the second backside spacers, in direct contact with the backside S/D contact via, and in direct contact with the backside gate contact via.
14. 14 . The semiconductor IC device of claim 8 , further comprising: a first plurality of inner spacers, each inner spacer of the first plurality of inner spacers in direct contact with at least one channel of the plurality of channels and in direct contact with the first S/D region; and a second plurality of inner spacers, each inner spacer of the second plurality of inner spacers in direct contact with at least one channel of the plurality of channels and in direct contact with the second S/D region.
15. 15 . The semiconductor IC device of claim 14 , wherein the first plurality of inner spacers and one of the first backside spacers are vertically inline and wherein the second plurality of inner spacers and one of the second backside spacers are vertically inline.
16. 16 . The semiconductor IC device of claim 8 , wherein a respective topmost surface of the first backside contact and the second backside contact are both below a bottommost channel of the plurality of channels.
17. 17 . The semiconductor IC device of claim 12 , wherein respective sidewalls of the first backside contact and respective sidewalls of the backside S/D contact via are directly connected to a respective one of the first backside spacers.
18. 18 . The semiconductor IC device of claim 12 , wherein the backside gate contact via is in direct contact with a sidewall of one of the first backside spacers and in direct contact with a sidewall of one of the second backside spacers.
19. 19 . A semiconductor integrated circuit (IC) device comprising: a first source/drain (S/D) region; a second S/D region; a first backside contact in direct contact with a backside of the first S/D region; a second backside contact in direct contact with a backside of the second S/D region; a first backside contact cap in direct contact with the first backside contact; a second backside contact cap in direct contact with the second backside contact; and a backside S/D contact via in direct contact with the first backside contact and in direct contact with the first backside contact cap.
20. 20 . The semiconductor IC device of claim 19 , further comprising: a backside gate contact via in direct contact with a gate, in direct contact with the first backside contact cap, and in direct contact with the second backside contact cap; and a backside back end of line (BEOL) network connected to the backside S/D contact via and connected to the backside gate contact via.

Description

BACKGROUND Some modern semiconductor integrated circuit (IC) devices utilize a direct backside contact (DBC) scheme. Typically, in this scheme, a backside contact placeholder is epitaxially grown prior to epitaxially growing a source/drain region thereupon. In order to more precisely control the epitaxial growth of the backside contact placeholders, typically, a respective backside contact placeholder is placed everywhere, or in each source/drain region canyon. Because there are some source/drain regions that do not utilize a backside contact, there are typically locations where the respective backside contact placeholders are retained. SUMMARY In an embodiment of the disclosure, a semiconductor integrated circuit (IC) device is presented. The device includes a backside contact in direct contact with a source/drain region, a backside contact cap in direct contact with the backside contact, a backside spacer in direct contact with respective sidewalls of the backside contact and the backside contact cap, and a backside S/D region contact via in direct contact with the backside contact, in direct contact with the backside spacer, and in direct contact with the backside contact cap. In another embodiment of the disclosure, another semiconductor IC device is presented. This device includes a plurality of channels each directly connected to a first source/drain (S/D) region and directly connected to a second S/D region, a first backside contact in direct contact with the first S/D region, and a second backside contact in direct contact with the second S/D region. This device further includes a first backside contact cap in direct contact with the first backside contact, a second backside contact cap in direct contact with the second backside contact, a first backside spacers in direct contact with respective sidewalls of the first backside contact and the first backside contact cap, and a second backside spacers in direct contact with respective sidewalls of the second backside contact and the second backside contact cap. This device further includes a backside gate contact via in direct contact with a gate, in direct contact with one of the first backside spacers, and in direct contact with one of the second backside spacers. In yet another embodiment of the disclosure, another semiconductor IC device is presented. This device includes a first source/drain (S/D) region, a second S/D region, a first backside contact in direct contact with a backside of the first S/D region, a second backside contact in direct contact with a backside of the second S/D region, a first backside contact cap in direct contact with the first backside contact, a second backside contact cap in direct contact with the second backside contact, and a backside S/D contact via in direct contact with the first backside contact and in direct contact with the first backside contact cap. The above summary is not intended to describe each illustrated embodiment or every implementation or example of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS The drawings included in the disclosure are incorporated into, and form part of, the specification. They illustrate embodiments of the present disclosure and, along with the description, explain the principles of the disclosure. The drawings are only illustrative of certain embodiments and do not limit the disclosure. FIG. 1A through FIG. 1C depict a cross-section view of illustrative semiconductor IC devices that includes capped backside contacts, according to one or more embodiments of the disclosure. FIG. 2 depicts a partial structure top-down view of an illustrative semiconductor IC device, according to one or more embodiments of the disclosure. FIG. 3 through FIG. 20 depict various fabrication structure cross-section views of an illustrative semiconductor IC device that is formed to include capped backside contacts, according to one or more embodiments of the disclosure. FIG. 21 depicts a method of fabricating a semiconductor IC device that includes capped backside contacts, according to one or more embodiments of the disclosure. DETAILED DESCRIPTION The embodiments of the present disclosure relate to fabrication methods and resulting structures for semiconductor IC devices. More specifically, the present disclosure relates to fabrication methods and resulting semiconductor integrated circuit (IC) devices that include capped backside contacts. This scheme may be utilized to form semiconductor IC devices without the traditional backside contact placeholders. A portion of the cap may be removed which may expose a corresponding portion of the backside contact. A backside contact via may be formed in direct connection with the exposed portion of the backside contact. Further, a cap associated with a backside contact may be adequately maintained and may adequately electrically isolate a backside gate contact via from the backside contact. A transistor is a type of microdevice that may be fabrica