US-20260129908-A1 - WRAPAROUND BACKSIDE CONTACT WITHIN RETAINED SUBSTRATE

Abstract

A semiconductor integrated circuit (IC) device is described. The device includes a transistor with a plurality of channels, a gate around each of the plurality of channels, a first source/drain (S/D) region, and a second S/D region. The device also includes a retained semiconductor substrate structure in direct contact with the first S/D region and with the second S/D region. The device further includes a wraparound backside contact in direct contact with the retained semiconductor substrate structure and in direct contact with the first S/D region.

Inventors

• Lijuan Zou
• Ruilong Xie
• Tao Li
• Oleg Gluschenkov
• Reinaldo Vega
• Ravikumar Ramachandran
• Kisik Choi

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260507

Application Date

20241101

Claims (20)

1. 1 . A semiconductor integrated circuit (IC) device comprising: a transistor comprising a plurality of channels, a gate around each of the plurality of channels, a first source/drain (S/D) region, and a second S/D region; a retained semiconductor substrate structure in direct contact with the first S/D region and with the second S/D region; and a wraparound backside contact in direct contact with the retained semiconductor substrate structure and in direct contact with the first S/D region.
2. 2 . The semiconductor IC device of claim 1 , wherein a backside surface of the first S/D region is below a frontside surface of the retained semiconductor substrate structure.
3. 3 . The semiconductor IC device of claim 1 , wherein a backside surface of the first S/D region is below a backside surface of the second S/D region.
4. 4 . The semiconductor IC device of claim 1 , wherein the wraparound backside contact is directly connected to three or more surfaces of the first S/D region.
5. 5 . The semiconductor IC device of claim 1 , further comprising: a backside contact plug in direct contact with the second S/D region and in direct contact with the retained semiconductor substrate structure.
6. 6 . The semiconductor IC device of claim 4 , wherein the wraparound backside contact is directly connected to a backside surface, a front wall, and a rear wall of the first S/D region.
7. 7 . The semiconductor IC device of claim 5 , further comprising: a backside back end of line (BEOL) network directly connected to the wraparound backside contact, directly connected to the backside contact plug, and directly connected to the retained semiconductor substrate structure.
8. 8 . The semiconductor IC device of claim 1 , further comprising: a frontside contact directly connected to the second S/D region.
9. 9 . The semiconductor IC device of claim 8 , further comprising: a frontside back end of line (BEOL) network directly connected to the frontside contact.
10. 10 . The semiconductor IC device of claim 1 , further comprising: a bottom inner spacer between the retained semiconductor substrate structure and a bottommost channel of the plurality of channels.
11. 11 . The semiconductor IC device of claim 1 , further comprising a shallow trench isolation (STI) region comprising a STI liner and an STI dielectric fill; wherein the first S/D region is in direct contact with the STI liner; and wherein the wraparound backside contact is in direct contact with the STI dielectric fill.
12. 12 . A semiconductor integrated circuit (IC) device comprising: a first source/drain (S/D) region; a second S/D region; a shallow trench isolation region (STI) in direct contact with the first S/D region and in direct contact with the second S/D region, the STI region comprising a STI liner and an STI dielectric fill; a retained semiconductor substrate structure in direct contact with the first S/D region, in direct contact with the second S/D region, and in direct contact with the STI region; and a wraparound backside contact in direct contact with the first S/D region and in direct contact with the retained semiconductor substrate structure.
13. 13 . The semiconductor IC device of claim 12 , further comprising: a backside contact plug in direct contact with the second S/D region and in direct contact with the retained semiconductor substrate structure.
14. 14 . The semiconductor IC device of claim 13 , wherein a backside surface of the first S/D region is below a backside surface of the second S/D region.
15. 15 . The semiconductor IC device of claim 14 , wherein the wraparound backside contact is directly connected to the backside surface of the first S/D region, a front wall of the first S/D region, and a rear wall of the first S/D region.
16. 16 . The semiconductor IC device of claim 15 , further comprising: a backside back end of line (BEOL) network directly connected to the wraparound backside contact, directly connected to a backside contact plug, and directly connected to the retained semiconductor substrate structure.
17. 17 . The semiconductor IC device of claim 16 , further comprising: a frontside contact directly connected to the second S/D region.
18. 18 . The semiconductor IC device of claim 17 , further comprising: a frontside back end of line (BEOL) network directly connected to the frontside contact.
19. 19 . The semiconductor IC device of claim 12 , further comprising: a bottom inner spacer between the retained semiconductor substrate structure and a bottommost channel of a plurality of channels.
20. 20 . A semiconductor integrated circuit (IC) device comprising: a plurality of channels above a retained semiconductor structure; a gate around each of the plurality of channels and upon the retained semiconductor structure; a first source/drain (S/D) region directly connected to the plurality of channels and directly connected to the retained semiconductor structure; a second S/D region directly connected to the plurality of channels and directly connected to the retained semiconductor structure; a wraparound backside contact in direct contact with the first S/D region and directly to the retained semiconductor structure; and a backside contact plug directly connected to the second S/D region and directly to the retained semiconductor structure.

Description

BACKGROUND The present disclosure relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present disclosure relates to fabrication methods and resulting semiconductor integrated circuit (IC) devices that include a wraparound backside contact within a retained semiconductor substrate structure. Conventional transistors, such as semiconductor IC devices, or the like, incorporate planar field effect transistors (FETs) in which current flows through a semiconducting channel between a source and a drain in response to a voltage applied to a control gate. The semiconductor industry strives to obey Moore's law, which holds that each successive generation of integrated circuit devices shrinks to half its size and operates twice as fast. As device dimensions have shrunk, however, conventional silicon device geometries and materials have had trouble maintaining switching speeds without incurring failures such as, for example, leaking current from the device into the semiconductor substrate. Several new technologies emerged that allowed chip designers to continue shrinking transistor sizes. A FET, generally, is a transistor in which output current, i.e., source-drain current, is controlled by a voltage applied to an associated gate. A FET typically has three terminals, i.e., a gate structure, a source region, and a drain region. A gate structure is a structure used to control output current (i.e., flow of carriers in the channel) of a semiconducting device through electrical or magnetic fields. A channel is the region of the FET underlying the gate structure and between the source and drain of the semiconductor IC device that becomes conductive when the semiconductor device is turned on. The source is a doped region in the semiconductor IC device, in which a majority carriers are flowing into the channel. A drain is a doped region in the semiconductor IC device located at the end of the channel, in which carriers are flowing out of the transistor through the drain. One technology change modified the structure of the FET from a planar device to a three-dimensional device in which the semiconducting channel was replaced by a fin that extends out from the plane of the substrate. In such a device, commonly referred to as a FinFET, the control gate wraps around three sides of the fin to influence current flow from three surfaces instead of one. The improved control achieved with a 3D design results in faster switching performance and reduced current leakage. Building taller devices has also permitted increasing the device density within the same footprint that had previously been occupied by a planar FET. The FinFET concept was further extended by developing a gate all-around FET, or GAA FET, in which the gate fully wraps around one or more channels for improved control of the current flow therein. In the GAA FET, the channels can take the form of nanolayers, nanosheets, or the like, which are isolated from the substrate. In the GAA FET, channel surfaces are in respective contact with the source and drain and other respective channel surfaces are in contact with and surrounded by the gate. SUMMARY In an embodiment of the present disclosure, a semiconductor integrated circuit (IC) device is presented. The device includes a transistor with a plurality of channels, a gate around each of the plurality of channels, a first source/drain (S/D) region, and a second S/D region. The device also includes a retained semiconductor substrate structure in direct contact with the first S/D region and with the second S/D region. The device further includes a wraparound backside contact in direct contact with the retained semiconductor substrate structure and in direct contact with the first S/D region. In an embodiment of the present disclosure, another semiconductor IC device is presented. The device includes a first source/drain (S/D) region, a second S/D region, a shallow trench isolation region (STI) in direct contact with the first S/D region and in direct contact with the second S/D region. The STI region includes a STI liner and an STI dielectric fill. The retained semiconductor substrate structure is in direct contact with the first S/D region, in direct contact with the second S/D region, and in direct contact with the STI region. The device further includes a wraparound backside contact in direct contact with the first S/D region and in direct contact with the retained semiconductor substrate structure. In an embodiment of the present disclosure, another semiconductor IC device is presented. The device includes a plurality of channels above a retained semiconductor structure. The device includes a gate around each of the plurality of channels and upon the retained semiconductor structure. The device includes a first source/drain (S/D) region directly connected to the plurality of channels and directly connected to the retained semiconductor structure. The device includes a second