US-20260129909-A1 - TRANSISTOR DEVICE WITH SELECTIVE THICK GATE DIELECTRIC AND METHOD

Abstract

Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include gate dielectrics in transistor devices with different thicknesses. Apparatus and methods are disclosed using a dopant to vary growth of gate dielectrics at desired locations within a semiconductor device.

Inventors

• Mandar Suresh Bhoir
• Salil Shashikant Mujumdar
• Uma Sharma

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260507

Application Date

20251103

Claims (20)

1. 1 . A semiconductor memory device, comprising: a transmission line, having a width and a thickness between a top surface and a bottom surface; a body region passing through the thickness of the transmission line within the width of the transmission line, wherein the body region includes a first source/drain region and a second source/drain region separated by a channel region; and a gate dielectric surrounding the body region and laterally separating the body region from the transmission line, wherein the gate dielectric varies in thickness with thicker regions adjacent to the top surface and the bottom surface.
2. 2 . The semiconductor memory device of claim 1 , wherein the first source/drain region and the second source/drain region are doped N-type, and the channel region is doped P-type.
3. 3 . The semiconductor memory device of claim 1 , wherein the first source/drain region and the second source/drain region are doped P-type, and the channel region is doped N-type.
4. 4 . The semiconductor memory device of claim 1 , wherein the gate dielectric includes an oxide material.
5. 5 . The semiconductor memory device of claim 1 , wherein a memory cell of the semiconductor memory device includes a 4F 2 form factor memory cell.
6. 6 . The semiconductor memory device of claim 1 , further including a storage capacitor coupled to the second source/drain region.
7. 7 . The semiconductor memory device of claim 1 , wherein the first source/drain region and the second source/drain region are at least partially located within the thickness of the transmission line
8. 8 . The semiconductor memory device of claim 1 , wherein the transmission line includes a wordline.
9. 9 . A semiconductor memory device, comprising: a transmission line, having a width and a thickness between a top surface and a bottom surface; a body region passing through the thickness of the transmission line within the width of the transmission line, wherein the body region includes a first source/drain region and a second source/drain region separated by a channel region; a gate oxide surrounding the body region and laterally separating the body region from the transmission line, wherein the gate oxide varies in thickness with thicker regions adjacent to the top surface and the bottom surface; and an oxide promoting dopant within the gate oxide.
10. 10 . The semiconductor memory device of claim 9 , wherein the oxide promoting dopant includes fluorine.
11. 11 . The semiconductor memory device of claim 9 , wherein the oxide promoting dopant includes argon.
12. 12 . The semiconductor memory device of claim 9 , wherein the oxide promoting dopant includes deuterium.
13. 13 . The semiconductor memory device of claim 9 , wherein the gate oxide includes silicon oxide.
14. 14 . The semiconductor memory device of claim 9 , wherein the gate oxide includes a transition metal oxide.
15. 15 . A method of forming a semiconductor device, comprising: forming a transistor body region on a semiconductor substrate; forming a transmission line around the transistor body region; doping with a dielectric promoting dopant within a region adjacent to opposing ends of the transistor body region, wherein a concentration of the dopant is higher adjacent to the opposing ends than in a middle of the transistor body region; forming a gate dielectric that surrounds the transistor body region, wherein; a central portion of the gate dielectric includes a first thickness; and end portions of the gate dielectric include a second thickness larger than the first thickness.
16. 16 . The method of claim 15 , wherein doping with a dielectric promoting dopant includes ion implantation of the dielectric promoting dopant.
17. 17 . The method of claim 15 , wherein doping with a dielectric promoting dopant includes depositing a doped material.
18. 18 . The method of claim 15 , wherein forming the transmission line includes forming a transmission line that includes polysilicon.
19. 19 . The method of claim 18 , wherein forming the transmission line includes forming multiple layers, wherein a top transmission line layer and a bottom transmission line layer are doped.
20. 20 . The method of claim 19 , wherein the transmission line is formed before the transistor body region, and wherein forming the gate dielectric includes oxidizing within an opening in the transmission line before filling the opening with the transistor body region.

Description

PRIORITY APPLICATION This application claims the benefit of priority to U.S. Provisional Application Ser. No. 63/717,015, filed Nov. 6, 2024, which is incorporated herein by reference in its entirety. BACKGROUND Memory devices are semiconductor circuits that provide electronic storage of data for a host system (e.g., a computer or other electronic device). Memory devices may be volatile or non-volatile. Volatile memory requires power to maintain data, and includes devices such as random-access memory (RAM), static random-access memory (SRAM), dynamic random-access memory (DRAM), or synchronous dynamic random-access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered, and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory, such as phase change random access memory (PCRAM), resistive random-access memory (RRAM), or magnetoresistive random access memory (MRAM), among others. Host systems typically include a host processor, a first amount of main memory (e.g., often volatile memory, such as DRAM) to support the host processor, and one or more storage systems (e.g., often non-volatile memory, such as flash memory) that provide additional storage to retain data in addition to or separate from the main memory. A storage system, such as a solid-state drive (SSD), can include a memory controller and one or more memory devices, including a number of dies or logical units (LUNs). In certain examples, each die can include a number of memory arrays and peripheral circuitry thereon, such as die logic or a die processor. The memory controller can include interface circuitry configured to communicate with a host device (e.g., the host processor or interface circuitry) through a communication interface (e.g., a bidirectional parallel or serial communication interface). The present description relates generally to transistor structures in complementary metal oxide semiconductor (CMOS) devices and manufacture. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document. FIG. 1 illustrates a memory device in accordance with some example embodiments. FIG. 2A illustrates a top view of a portion of a memory device in accordance with some example embodiments. FIG. 2B illustrates an isometric view of the portion from FIG. 2 in accordance with some example embodiments. FIG. 3 illustrates a cross section view of a portion of a memory device in accordance with some example embodiments. FIG. 4A illustrates another cross section view of a portion of a memory device in accordance with some example embodiments. FIG. 4B illustrates another cross section view of a portion of a memory device in accordance with some example embodiments. FIG. 5 illustrates a plot of gate dielectric thicknesses versus dopant dose in accordance with some example embodiments. FIG. 6 illustrates an example method flow diagram in accordance with other example embodiments. FIG. 7 illustrates an example block diagram of an information handling system in accordance with some example embodiments. DETAILED DESCRIPTION The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims. FIG. 1 shows a block diagram of an apparatus in the form of a memory device 100, according to an embodiment of the invention. Memory device 100 can include transistors with gate oxide configurations that have different thicknesses as described in more detail below. Memory device 100 can include a memory array 102 having memory cells 103 that can be arranged in rows and columns along with lines (e.g., access lines) 104 and lines (e.g., data lines) 105. Memory device 100 can use lines 104 to access memory cells 103 and lines 105 to exchange information with memory cells 103. Memory cells 103 and other circuits 114, 116, etc. may include transistors and utilize methods as described in more detail in FIGS. 2-7. In one example, memory arrays 102 include NAND storage array, and peripheral circuits such as circuits 114, 116, 108, 109, etc. may include transistors as described in more detail in FIGS. 2-7. One example of a peripheral circuit that utilizes transistors as described includes a string driver circuit, although the invention is not so