US-20260129911-A1 - DISPLAY MODULE INCLUDING ZINC-BASED BARRIER PATTERN AND METHOD FOR MANUFACTURING SAME

US20260129911A1US 20260129911 A1US20260129911 A1US 20260129911A1US-20260129911-A1

Abstract

A display module includes a substrate; a semiconductor pattern provided on the substrate and including a gate region, a drain region, and a source region; a first insulating layer provided on the substrate, and covering a region of the semiconductor pattern other than the drain region and the source region; a gate electrode provided on a region of the first insulating layer corresponding to the gate region of the semiconductor pattern; a second insulating layer provided on the first insulating layer and covering the gate electrode; a first barrier pattern provided on the drain region; a second barrier pattern provided on the source region; a drain electrode provided on the first barrier pattern; and a source electrode provided on the second barrier pattern.

Inventors

Donggun OH
Jinho Kim
Chulgyu Jung
Tetsuya Shigeta

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251114
Priority Date: 20200403

Claims (9)

1 . A display module comprising: a substrate; a semiconductor pattern provided on the substrate and comprising a gate region, a drain region, and a source region; a first insulating layer provided on the substrate, and covering a region of the semiconductor pattern other than the drain region and the source region; a gate electrode provided on a region of the first insulating layer corresponding to the gate region of the semiconductor pattern; a second insulating layer provided on the first insulating layer and covering the gate electrode; a first barrier pattern provided on the drain region; a second barrier pattern provided on the source region; a drain electrode provided on the first barrier pattern; and a source electrode provided on the second barrier pattern.
2 . The display module of claim 1 , wherein the drain electrode and the source electrode comprise copper (Cu), and the first barrier pattern and the second barrier pattern comprise a zinc-based (Zn-based) alloy comprising titanium (Ti).
3 . The display module of claim 1 , wherein the Zn-based alloy comprises zinc (Zn) having a content greater than or equal to 90wt % and the Ti.
4 . The display module of claim 1 , wherein the Zn-based alloy has a thickness in a range of 50 Å to 500Å.
5 . The display module of claim 1 , wherein the first barrier pattern and the second barrier pattern surround a sidewall of the first insulating layer and the second insulating layer on the drain region and the source region, respectively.
6 . The display module of claim 1 , wherein the semiconductor pattern comprises low temperature poly silicon (LTPS).
7 . The display module of claim 1 , further comprising: a buffer layer formed between the substrate and the semiconductor pattern to block diffusion of a material included in the substrate into the semiconductor pattern.
8 . The display module of claim 1 , further comprising: a pixel electrode formed on the drain electrode; and a micro-LED formed on the pixel electrode such that the micro-LED is connected to the pixel electrode and a common electrode separated from the pixel electrode.
9 . The display module of claim 1 , further comprising: a protective layer formed on the second insulating layer to cover the drain electrode and the source electrode.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application is a divisional of U.S. application Ser. No. 17/945,770, filed on Sep. 15, 2022, which is a continuation application of International Application No. PCT/KR 2021/004124, filed on Apr. 2, 2021, which is based on and claims priority to Korean Patent Application No. 10-2020-0041216, filed on Apr. 3, 2020, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties. BACKGROUND 1. Field This disclosure relates to a display module and a method for manufacturing the same, and more particularly, to a display module and a method for manufacturing the same. 2. Description of Related Art A thin film transistor (TFT) controls driving of a pixel in a display device. Here, the pixels are composed of sub-pixels, and the pixels may represent various colors through a combination of the color and luminance of light represented by the sub-pixels. For fast change of a screen of a display device, it may be required that a TFT controlling each pixel quickly reacts and operates. In the case of a display device using a self-emitting element such as an organic light emitting element or an inorganic light emitting element as a pixel, high current driving of the TFT may be required for excellent luminance characteristics (e.g., high luminance, uniform luminance, etc.). When the electrical resistance of a material used for wiring (or electrode) of the TFT is high, there is a problem that voltage drop occurs. In this example, there is a problem in that a flicker phenomenon in which luminance of a pixel is not constant, changes, and vibrates, and luminance deviation indicating a difference between an average value of the luminance measured in the entire or partial screen area of the display device and the luminance measured in a specific area, and in particular, as the size of the display becomes large, this phenomenon may get worsen. If copper (Cu) having low electrical resistance is used for wiring of TFT, there may be a problem in that the characteristic of TFT may be degraded due to contamination of the copper. SUMMARY Provided are a display module for driving a pixel and a manufacturing method thereof. According to an aspect of the disclosure, a method of manufacturing a display module includes: forming a semiconductor pattern on a substrate; forming a first insulating layer covering the semiconductor pattern on the substrate; forming a gate electrode on a region of the first insulating layer corresponding to a gate region of the semiconductor pattern; forming a second insulating layer covering the gate electrode on the first insulating layer; forming a first hole passing through the first insulating layer and the second insulating layer to expose a drain region of the semiconductor pattern and forming a second hole passing through the first insulating layer and the second insulating layer to expose a source region of the semiconductor pattern; and forming a first barrier pattern on the drain region in the first hole and a second barrier pattern on the source region in the second hole, and forming a drain electrode on the first barrier pattern and a source electrode on the second barrier pattern. The drain electrode and the source electrode may include Cu, and the first barrier pattern and the second barrier pattern may include Zn-based alloy. The Zn-based alloy may include Zn having content greater than or equal to 90wt % and at least one of Ti, Mo, Au, Al, Mg, Sn, and Sb. The Zn-based alloy may have a thickness in a range of 50 Å to 500 Å. The forming the first barrier pattern, the second barrier pattern, the drain electrode, and the source electrode may include: forming a barrier layer on the second insulating layer in which the first hole and the second hole are formed; forming an electrode layer on the barrier layer; and forming the first barrier pattern, the second barrier pattern, the drain electrode and the source electrode by patterning the barrier layer and the electrode layer simultaneously. The patterning the barrier layer and the electrode layer simultaneously may include performing a photolithography process. The forming the electrode layer may include, after forming the barrier layer, forming the electrode layer in the barrier layer consecutively in a chamber to prevent oxidation of the first barrier pattern and the second barrier pattern. The semiconductor pattern may include low temperature poly silicon (LTPS), and the forming the semiconductor pattern may include: forming a buffer layer to block diffusion of a material included in the substrate into the semiconductor pattern on the substrate; depositing amorphous silicon (a-Si) on the buffer layer; and forming the LTPS with changed crystalline arrangement of the a-Si by irradiating the a-Si with a laser. The method may further include: forming a pixel electrode on the drain electrode; and bonding a micro light emitting diode on the pixel ele