US-20260129912-A1 - ACCESS TRANSISTOR INCLUDING A METAL OXIDE BARRIER LAYER AND METHODS FOR FORMING THE SAME

Abstract

A transistor may be provided by forming, in a forward order or in a reverse order, a gate electrode, a metal oxide liner, a gate dielectric, and an active layer over a substrate, and by forming a source electrode and a drain electrode on end portions of the active layer. The metal oxide liner comprises a thin semiconducting metal oxide material that functions as a hydrogen barrier material.

Inventors

• Mauricio Manfrini
• Marcus Johannes Henricus Van Dal
• Georgios Vellianitis
• Gerben Doornbos

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Dates

Publication Date

20260507

Application Date

20251229

Claims (20)

1. 1 . A semiconductor structure, comprising: an insulating layer overlying a substrate; a word line in the insulating layer; a gate electrode attached to a top surface of the word line; a hydrogen-containing conductive planar metal oxide liner overlying and contacting the gate electrode and the insulating layer; a gate dielectric overlying the hydrogen-containing conductive planar metal oxide liner; an active layer overlying the gate dielectric; and a source electrode and a drain electrode contacting respective end portions of the active layer.
2. 2 . The semiconductor structure of claim 1 , wherein the hydrogen-containing conductive planar metal oxide liner comprises sidewalls that are vertically coincident with sidewalls of the active layer.
3. 3 . The semiconductor structure of claim 1 , wherein the hydrogen-containing conductive planar metal oxide liner is a remaining portion of a continuous semiconducting metal oxide layer and is located entirely below a horizontal plane including a top surface of the insulating layer, the remaining portion forming a hydrogen-containing conductive metal oxide liner that is a ternary compound selected from indium gallium zinc oxide, indium tungsten oxide, indium zinc oxide, or indium tin oxide.
4. 4 . The semiconductor structure of claim 1 , wherein the hydrogen-containing conductive planar metal oxide liner has a thickness in a range from 0.1 nm to 3 nm and the active layer has a thickness that is at least three times a thickness of the hydrogen-containing conductive planar metal oxide liner.
5. 5 . The semiconductor structure of claim 1 , wherein the hydrogen-containing conductive planar metal oxide liner comprises a horizontal surface that contacts an entirety of a horizontal surface of the gate dielectric.
6. 6 . The semiconductor structure of claim 1 , wherein the hydrogen-containing conductive planar metal oxide liner comprises a region that laterally extends outside a periphery of the active layer in a plan view.
7. 7 . The semiconductor structure of claim 1 , further comprising a hydrogen-containing conductive conformal metal oxide liner disposed on the word line and the insulating layer and laterally surrounding the gate electrode, wherein the gate electrode overlies and contacts the hydrogen-containing conductive conformal metal oxide liner.
8. 8 . A semiconductor structure, comprising: an insulating layer overlying a substrate and having a top surface; a gate cavity in an upper portion of the insulating layer; a word line beneath the gate cavity; a gate electrode attached to a top surface of the word line and disposed within the gate cavity; a hydrogen-containing conductive metal oxide liner located in the gate cavity and contacting the gate electrode and the insulating layer; a gate dielectric overlying the gate electrode; an active layer overlying the gate dielectric; and a source electrode and a drain electrode contacting respective end portions of the active layer.
9. 9 . The semiconductor structure of claim 8 , wherein the hydrogen-containing conductive metal oxide liner is a remaining portion of a continuous semiconducting metal oxide layer and is located within a volume of the gate cavity and below a horizontal plane including the top surface of the insulating layer, the remaining portion forming a hydrogen-containing conductive metal oxide liner that is a ternary compound selected from indium gallium zinc oxide, indium tungsten oxide, indium zinc oxide, or indium tin oxide.
10. 10 . The semiconductor structure of claim 8 , wherein the hydrogen-containing conductive metal oxide liner comprises sidewalls that are vertically coincident with sidewalls of the active layer.
11. 11 . The semiconductor structure of claim 8 , wherein a top surface of the gate electrode is substantially coplanar with the top surface of the insulating layer, and wherein the hydrogen-containing conductive metal oxide liner has a thickness in a range from 0.1 nm to 3 nm and the active layer has a thickness that is at least three times the thickness of the hydrogen-containing conductive metal oxide liner.
12. 12 . The semiconductor structure of claim 8 , wherein the hydrogen-containing conductive metal oxide liner comprises a horizontal surface that contacts an entirety of a horizontal surface of the gate dielectric.
13. 13 . The semiconductor structure of claim 8 , further comprising a memory element electrically coupled to the drain electrode.
14. 14 . The semiconductor structure of claim 8 , further comprising a hydrogen-containing conductive conformal metal oxide liner disposed in the gate cavity on the insulating layer and the word line, wherein the gate electrode overlies and contacts the hydrogen-containing conductive conformal metal oxide liner.
15. 15 . A semiconductor structure, comprising: an insulating layer overlying a substrate; a word line formed within the insulating layer; a hydrogen-containing conductive conformal metal oxide liner disposed on the word line and the insulating layer; a gate electrode overlying and directly on the hydrogen-containing conductive conformal metal oxide liner; a hydrogen-containing conductive planar metal oxide liner overlying the hydrogen-containing conductive conformal metal oxide liner; a gate dielectric overlying the hydrogen-containing conductive planar metal oxide liner; an active layer overlying the gate dielectric; and a source electrode and a drain electrode contacting respective end portions of the active layer.
16. 16 . The semiconductor structure of claim 15 , wherein the hydrogen-containing conductive planar metal oxide liner comprises sidewalls that are vertically coincident with sidewalls of the active layer.
17. 17 . The semiconductor structure of claim 15 , wherein the hydrogen-containing conductive planar metal oxide liner is a remaining portion of a continuous semiconducting metal oxide layer and is located entirely below a horizontal plane including a top surface of the insulating layer, the remaining portion forming a hydrogen-containing conductive metal oxide liner that is a ternary compound selected from indium gallium zinc oxide, indium tungsten oxide, indium zinc oxide, or indium tin oxide.
18. 18 . The semiconductor structure of claim 15 , wherein the hydrogen-containing conductive planar metal oxide liner has a thickness in a range from 0.1 nm to 3 nm and the active layer has a thickness that is at least three times the thickness of the hydrogen-containing conductive planar metal oxide liner.
19. 19 . The semiconductor structure of claim 15 , wherein each of the hydrogen-containing conductive conformal metal oxide liner and the hydrogen-containing conductive planar metal oxide liner comprises a semiconducting metal oxide selected from indium gallium zinc oxide, indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, or doped cadmium oxide.
20. 20 . The semiconductor structure of claim 15 , further comprising a memory element electrically coupled to the drain electrode.

Description

RELATED APPLICATIONS This application is a continuation application of U.S. application Ser. No. 17/485,848 titled “Access Transistor Including a Metal Oxide Barrier Layer and Methods for Forming the Same” and filed on Sep. 27, 2021, which claims the benefit of priority from a U.S. provisional application Ser. No. 63/189,945, entitled “Barrier layer for work function engineering in TFTs,” filed on May 18, 2021, the entire contents of all of which are incorporated herein by reference for all purposes. BACKGROUND A variety of transistor structures have been developed to meet various design criteria. Thin film transistors (TFT) made of oxide semiconductors are an attractive option for back-end-of-line (BEOL) integration since TFTs may be processed at low temperatures and thus, will not damage previously fabricated devices. For example, the fabrication conditions and techniques do not damage previously fabricated front-end-of-line (FEOL) and middle end-of-line (MEOL) devices. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a vertical cross-sectional view of a first exemplary structure after formation of complementary metal-oxide-semiconductor (CMOS) transistors, first metal interconnect structures formed in lower-level dielectric material layers, and an isolation dielectric layer according to an embodiment of the present disclosure. FIG. 2A is a top-down view of a region of the first exemplary structure after formation of a body bias line according to a first embodiment of the present disclosure. FIG. 2B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of FIG. 2A. FIG. 2C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C-C′ of FIG. 2A. FIG. 3A is a top-down view of the region of the first exemplary structure after formation of an insulating layer and a body contact cavity according to the first embodiment of the present disclosure. FIG. 3B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of FIG. 3A. FIG. 3C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C-C′ of FIG. 3A. FIG. 4A is a top-down view of the region of the first exemplary structure after formation of a body contact via structure according to the first embodiment of the present disclosure. FIG. 4B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of FIG. 4A. FIG. 4C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C-C′ of FIG. 4A. FIG. 5A is a top-down view of the region of the first exemplary structure after formation of a continuous active layer and a top gate dielectric layer according to the first embodiment of the present disclosure. FIG. 5B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of FIG. 5A. FIG. 5C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C-C′ of FIG. 5A. FIG. 6A is a top-down view of the region of the first exemplary structure after formation of a stack of a top gate dielectric and an active layer according to the first embodiment of the present disclosure. FIG. 6B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of FIG. 6A. FIG. 6C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C-C′ of FIG. 6A. FIG. 7A is a top-down view of the region of the first exemplary structure after formation of a dielectric layer according to the first embodiment of the present disclosure. FIG. 7B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of FIG. 7A. FIG. 7C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C-C′ of FIG. 7A. FIG. 8A is a top-down view of the region of the first exemplary structure after formation of a source cavity and a drain cavity according to the first embodiment of the present disclosure. FIG. 8B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of FIG. 8A. FIG. 8C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C-C′ of FIG. 8A. FIG. 9A is a top-down view of the region of the first exemplary structure after formation of a source electrode and a drain electrode according to the first embodiment of the present disclosure. FIG. 9B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of