US-20260129916-A1 - FLOATING GATE SEPARATING ADJACENT TERMINALS OF CIRCUIT TRANSISTOR

Abstract

An integrated circuit can include a semiconductor substrate and a field-effect transistor (FET) formed in or on an active area of the substrate. The FET can include a first drain or source region of a specific terminal type, and a second drain or source region of the same terminal type, located adjacent to but physically separated from the first drain or source region. Such regions can be electrically connected via a first electrical conductor path. The FET can include a first floating gate region situated between the first and second drain or source regions. A third drain or source region, of a different terminal type than the first and second regions, is also included and is electrically connected via a second electrical conductor path. A first electrically interconnected gate region can be disposed between the first drain or source region and the third drain or source region.

Inventors

• Adalberto Cantoni
• Lawrence A. Singer

Assignees

• ANALOG DEVICES, INC.

Dates

Publication Date

20260507

Application Date

20241104

Claims (19)

1. 1 . An integrated circuit comprising: a semiconductor substrate; and a field-effect transistor (FET), formed in or on an active area of the substrate, the field-effect transistor comprising: a first drain or source region, being one of a drain terminal type or a source terminal type; a second drain or source region, of the same terminal type as the first drain or source region, located adjacent to but physically separated from the first drain or source region, the second drain or source region electrically connected to the first drain or source region via a first electrical conductor path; a first floating gate region, located between the first drain or source region and the second drain or source region; a third drain or source region, of a different terminal type than the first and second drain or source regions, the third drain or source region electrically connected via a second electrical conductor path; and a first electrically interconnected gate region located between the first drain or source region and the third drain or source region.
2. 2 . The integrated circuit of claim 1 , further comprising: a fourth drain or source region, of the same terminal type as the third drain or source region, located adjacent to but physically separated from the third drain or source region, the fourth drain or source region electrically connected to the third drain or source region, via the second electrical conductor path; and a second floating gate region, located between the third drain or source region and the fourth drain or source region.
3. 3 . The integrated circuit of claim 1 , comprising: a second electrically interconnected gate region; wherein: the first floating gate region is located between the first electrically interconnected gate region and the second electrically interconnected gate region; and a distance between the first electrically interconnected gate region and the second electrically interconnected gate region is within a range of 1.5 times and 5 times a specified integrated circuit manufacturing process minimum gate-to-gate pitch parameter.
4. 4 . The integrated circuit of claim 3 , wherein a distance between the first floating gate region and each of the first and second electrically interconnected gate regions is within a range of 1 times to 2.5 times a specified integrated circuit manufacturing process minimum gate-to-gate pitch parameter.
5. 5 . The integrated circuit of claim 1 , wherein the first floating gate is electrically unbiased by electrical charge tunneled and stored onto the first floating gate.
6. 6 . The integrated circuit of claim 1 , wherein the first floating gate is not accessible by any control gate.
7. 7 . The integrated circuit of claim 1 , wherein the first floating gate region is formed of a material including polysilicon.
8. 8 . The integrated circuit of claim 1 , wherein the FET includes a FinFET.
9. 9 . The integrated circuit of claim 1 , further comprising: a fourth drain or source region, of the same terminal type as the first and second drain or source regions, physically separated from the third drain or source region, and electrically connected to the first and second drain or source regions; and a second electrically interconnected gate region located between the third drain or source region and the fourth drain or source region.
10. 10 . The integrated circuit of claim 9 , further comprising: a fifth drain or source region, of the same terminal type as the fourth drain or source region, located adjacent to but physically separated from the fourth drain or source region, the fifth drain or source region electrically connected to the fourth drain or source region; and a second floating gate region, located between the fourth drain or source region and the fifth drain or source region.
11. 11 . An integrated circuit comprising: a semiconductor substrate; and a plurality of field-effect transistors (FETs), formed in or on an active area of the substrate, an individual FET comprising: a first drain or source region, being one of a drain terminal type or a source terminal type; a second drain or source region, of the same terminal type as the first drain or source region, located adjacent to but physically separated from the first drain or source region, the second drain or source region electrically connected to the first drain or source region via a first electrical conductor path; a first floating gate region, located between the first drain or source region and the second drain or source region; a third drain or source region, of a different terminal type than the first and second drain or source regions, the third drain or source region electrically connected via a second electrical conductor path; and a first electrically interconnected gate region located between the first drain or source region and the third drain or source region; wherein the plurality of FETs are arranged in or on the substrate as an at least one-dimensional array of transistors.
12. 12 . The integrated circuit of claim 11 , further comprising: a fourth drain or source region, of the same terminal type as the third drain or source region, located adjacent to but physically separated from the third drain or source region, the fourth drain or source region electrically connected to the third drain or source region, via the second electrical conductor path; and a second floating gate region, located between the third drain or source region and the fourth drain or source region.
13. 13 . The integrated circuit of claim 11 , comprising: a second electrically interconnected gate region; wherein: the first floating gate region is located between the first electrically interconnected gate region and the second electrically interconnected gate region; and a distance between the first electrically interconnected gate region and the second electrically interconnected gate region is within a range of 1.5 times and 5 times a specified integrated circuit manufacturing process minimum gate-to-gate pitch parameter.
14. 14 . The integrated circuit of claim 13 , wherein a distance between the first floating gate region and each of the first and second electrically interconnected gate regions within a range of 1 times to 2.5 times a specified integrated circuit manufacturing process minimum gate-to-gate pitch parameter.
15. 15 . The integrated circuit of claim 11 , wherein: the first and second drain or source regions extend as fingers parallel to each other and are electrically interconnected to each other via first electrical conductor path; and the third drain or source region extends parallel to the first and second drain or source regions and are electrically interconnected to each other via the second electrical conductor path.
16. 16 . The integrated circuit of claim 11 , wherein the first floating gate is electrically unbiased by electrical charge tunneled and stored onto the first floating gate.
17. 17 . A method of manufacturing an integrated circuit, the method comprising: forming active areas, corresponding with a plurality of field effect transistors (FETs), on a semiconductor substrate of the integrated circuit; and forming the FETs by forming drain and source regions in the active areas and forming gate regions, including, for an individual FET: forming a first drain or source region, being one of a drain terminal type or a source terminal type; forming a second drain or source region, of the same terminal type as the first drain or source region, located adjacent to but physically separated from the first drain or source region, the second drain or source region electrically connected to the first drain or source region via a first electrical conductor path; disposing a first floating gate region between the first drain or source region and the second drain or source region; forming a third drain or source region, of a different terminal type than the first and second drain or source regions, the third drain or source region electrically connected via a second electrical conductor path; and disposing a first electrically interconnected gate region between the first drain or source region and the third drain or source region.
18. 18 . The method of claim 17 , wherein the forming the FETs includes: forming n-type FETs; forming alternatingly arranged n-type circuit FETs and n-type floating FETs.
19. 19 . The method of claim 17 , wherein the forming the FETs includes: forming p-type FETs; forming alternatingly arranged p-type circuit FETs and p-type floating FETs.

Description

BACKGROUND Field-effect transistors (FETs) are fundamental components in many electronic devices, serving as the building blocks in integrated circuits. FETs can operate by controlling the flow of electrical current within a semiconductor path, such as for amplifying signals or switching electronic signals on and off. The performance of FETs can be significantly influenced by the physical and electrical properties of their constituent materials and the geometric configuration of their source, drain, and gate regions. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, which are not necessarily drawn to scale, like numerals can describe similar components in different views. Like numerals having different letter suffixes can represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document. FIG. 1 is a cross-sectional view of an example of a transistor of an integrated circuit (IC), showing a stack of transistor contacts and metal traces. FIG. 2A is a diagram of an example of a multi-finger transistor including an alternating row of source and drain contacts. FIG. 2B is a diagram of an example of a multi-finger transistor including multiple successive source or drain contacts in a row of alternating source and drain contacts. FIG. 2C is a diagram of an example of a multi-finger transistor including floating gates disposed between multiple successive source or drain contacts, within in a row of alternating source and drain contacts. FIG. 2D is a diagram of an example of a multi-finger transistor including off-biased gates disposed between multiple successive source or drain contacts in a row of alternating source and drain contacts. FIG. 2E is a schematic diagram showing a resistance between exemplary drain and source contacts and respective capacitances between exemplary a gate and source contact and between a gate and drain contact. FIG. 2F is a diagram of an example of a multi-finger transistor including floating gates disposed between multiple successive source or drain contacts, within in a row of alternating source and drain contacts. FIG. 2G is a schematic diagram showing effects of floating gates on a resistance between drain and source contacts and respective capacitances between a gate and source contact and between a gate and drain contact. FIG. 3A is a diagram of an example of a multi-finger transistor including floating gates disposed between multiple successive source or drain contacts, within in a row of alternating source and drain contacts. FIG. 3B is a diagram of an example of a multi-finger transistor including floating gates disposed between multiple successive source or drain contacts, within in a row of alternating source and drain contacts. FIG. 3C is a diagram of an example of a multi-finger transistor including floating gates disposed between multiple successive source, within in a row of alternating source and drain contacts. FIG. 3D is a diagram of an example of a multi-finger transistor including floating gates disposed between multiple successive source, within in a row of alternating source and drain contacts. FIG. 3E is a diagram of an example of a multi-finger transistor including floating gates disposed between multiple successive drain contacts, within in a row of alternating source and drain contacts. FIG. 3F is a diagram of an example of a multi-finger transistor including floating gates disposed between multiple successive drain contacts, within in a row of alternating source and drain contacts. FIG. 4A is a diagram of an example of a multi-finger transistor including floating gates disposed between multiple successive source or drain contacts, within in a row of alternating source and drain contacts. FIG. 4B is a diagram of an example of a multi-finger transistor including floating gates disposed between multiple successive source or drain contacts, within in a row of alternating source and drain contacts. FIG. 4C is a diagram of an example of a multi-finger transistor including floating gates disposed between multiple successive source or drain contacts, within in a row of alternating source and drain contacts. FIG. 5 is a flowchart showing an exemplary method of making an integrated circuit, including field-effect transistors (FETs) with a floating gate disposed between multiple successive source or drain contacts. DETAILED DESCRIPTION The performance of field-effect transistors (FETs) can be significantly influenced by the physical and electrical properties of their constituent materials and the geometric configuration of their source, drain, and gate regions. It can be desirable in semiconductor fabrication (e.g., during a front end of line (FEOL) or mid end of line (MEOL) process) to scale down certain FET dimensions, such as to develop toward increasing a density and performance of a particular integrated circuit (IC) die or chip. Such scaling,