US-20260129917-A1 - TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

US20260129917A1US 20260129917 A1US20260129917 A1US 20260129917A1US-20260129917-A1

Abstract

Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.

Inventors

Yu-Chu Lin
Wen-Chih Chiang
Chi-Chung JEN
Ming-Hong Su
Mei-Chen Su
Chia-Wei Lee
Kuan-Wei SU
Chia-Ming PAN

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20260105

Claims (20)

1 . A semiconductor structure, comprising: a first terminal on a substrate of the semiconductor structure, the first terminal comprising: a first portion of a tunneling layer formed on the substrate, and a first conductive structure formed on the first portion of the tunneling layer; a second terminal on the substrate, the second terminal comprising: a second portion of the tunneling layer formed on the substrate, a second conductive structure formed on the second portion of the tunneling layer, and a dielectric structure formed on the second conductive structure; a lightly doped drain portion included in the substrate, wherein the lightly doped drain portion is disposed under at least a portion of the first conductive structure and at least a portion of the second conductive structure; and a doped portion included in the substrate under the lightly doped drain portion and having a conductivity that is different from a conductivity of the lightly doped drain portion.
2 . The semiconductor structure of claim 1 , wherein the dielectric structure is formed between a side of the first conductive structure and a side of the second conductive structure.
3 . The semiconductor structure of claim 1 , wherein the dielectric structure is formed on a top surface of the second conductive structure.
4 . The semiconductor structure of claim 1 , wherein the lightly doped drain portion and the doped portion are adjacent to a source/drain region.
5 . The semiconductor structure of claim 1 , further comprising a third terminal coupled to an insulating structure of the semiconductor structure, wherein the third terminal comprises a third conductive structure adjacent to the second conductive structure.
6 . The semiconductor structure of claim 5 , wherein the dielectric structure is formed between a side of the third conductive structure and a side of the second conductive structure.
7 . The semiconductor structure of claim 5 , wherein the insulating structure comprises: a shallow trench isolation structure, a deep trench isolation structure, or an insulating material disposed on a top surface of the substrate.
8 . The semiconductor structure of claim 1 , wherein the first conductive structure and a top portion of the dielectric structure extend to approximately a same height relative to a top surface of the substrate of the semiconductor structure.
9 . The semiconductor structure of claim 1 , wherein a portion of the dielectric structure is disposed between the first portion of a tunneling layer and the second portion of the tunneling layer.
10 . A semiconductor structure, comprising: a substrate; a doped portion in the substrate; a lightly doped drain portion in the substrate over the doped portion; a tunneling layer on the substrate, wherein the tunneling layer comprises a first portion and a second portion; a first conductive structure on the first portion of the tunneling layer; a second conductive structure on the second portion of the tunneling layer, wherein at least a portion of the first conductive structure and at least a portion of the second conductive structure are disposed over the lightly doped drain portion; and a dielectric structure on a top surface and on side surfaces of the second conductive structure, wherein a portion of the dielectric structure is disposed between a side surface of the first conductive structure and a side surface of the side surfaces of the second conductive structure.
11 . The semiconductor structure of claim 10 , wherein at least part of the first portion of the tunneling layer and at least part of the second portion of the tunneling layer are disposed over the lightly doped drain portion.
12 . The semiconductor structure of claim 10 , wherein part of the portion of the dielectric structure is disposed between the first portion of the tunneling layer and the second portion of the tunneling layer.
13 . The semiconductor structure of claim 10 , further comprising: an insulating structure in the substrate; and a third conductive structure on the insulating structure, wherein an additional portion of the dielectric structure is disposed between a side surface of the third conductive structure and an additional side surface of the side surfaces of the second conductive structure.
14 . The semiconductor structure of claim 13 , wherein the insulating structure is on a side of the doped portion and the lightly doped drain portion.
15 . The semiconductor structure of claim 10 , wherein the dielectric structure is formed in a U-shape around the second conductive structure.
16 . A semiconductor structure, comprising: a substrate; a lightly doped drain portion and a doped portion in the substrate, wherein the doped portion is directly under the lightly doped drain portion, and wherein a conductivity of the doped portion is higher than a conductivity of the lightly doped drain portion; a tunneling layer on the substrate, wherein the tunneling layer includes a first portion and a second portion; a first conductive structure on the first portion of the tunneling layer, wherein the first conductive structure is disposed over a first part of the lightly doped drain portion; a second conductive structure on the second portion of the tunneling layer, wherein the second conductive structure is disposed over a second part of the lightly doped drain portion; and a dielectric structure disposed around the second conductive structure, wherein the dielectric structure is disposed between a side surface of the first conductive structure and a side surface of the second conductive structure.
17 . The semiconductor structure of claim 16 , further comprising: a third conductive structure on the substrate, wherein the third conductive structure is adjacent to the second conductive structure, and wherein the dielectric structure is further disposed between a side surface of the third conductive structure and an additional side surface of the second conductive structure.
18 . The semiconductor structure of claim 17 , wherein the first conductive structure, a top portion of the dielectric structure, and the third conductive structure are at approximately a same height relative to a top surface of the substrate.
19 . The semiconductor structure of claim 16 , further comprising a source/drain region in the substrate adjacent to the doped portion and to the lightly doped drain portion.
20 . The semiconductor structure of claim 16 , further comprising: a first electrical connector on the first conductive structure; and a second electrical connector on the dielectric structure, wherein the first electrical connector and the second electrical connector are at approximately a same height relative to a top surface of the substrate.

Description

RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 18/752,086, filed Jun. 24, 2024, which is a divisional of U.S. patent application Ser. No. 17/446,546, filed Aug. 31, 2021 (now U.S. Pat. No. 12,051,755), the contents of each of which are incorporated herein by reference in their entireties. BACKGROUND A transistor is a common type of semiconductor device in electronic devices that is able to amplify and/or switch electrical signals. A transistor may be configured with multiple terminals to receive one or more applications of voltage. A voltage applied to a first terminal associated with a gate may control a current across a second terminal associated with a source voltage and a third terminal associated with a drain voltage. The transistor may be configured to perform different operations based on applications of different combinations of voltages to the terminals. For example, the transistor may perform a programming operation, a read operation, or an erase operation when different combinations of voltages are applied to the terminals of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a diagram of an example environment in which systems and/or methods described herein may be implemented. FIG. 2 is a diagram of an example semiconductor structure described herein. FIGS. 3A-3H are diagrams of an example implementation described herein. FIG. 4 is a diagram of an example semiconductor structure described herein. FIG. 5 is a diagram of example components of one or more devices of FIG. 1. FIG. 6 is a flowchart of an example process relating to forming a semiconductor structure described herein. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In some cases, a semiconductor structure may include a gate structure that includes a control gate and a floating gate in a stacked configuration. Based on the gate structure being in a stacked configuration, the gate structure may extend to a height above a substrate of the semiconductor structure that is relatively high (e.g., in comparison with another device, such as a logic device disposed in a same level of the semiconductor structure). The height of the gate structure being relatively high may cause an increased likelihood of deterioration of a dielectric structure disposed between a top surface of the gate structure and an electrode that provides a voltage to the gate structure (e.g., based on a decreased thickness of the dielectric structure), which may cause shorting and/or other failures of the semiconductor structure. Additionally, or alternatively, the stacked configuration may provide a stress on a tunneling oxide material disposed between the gate structure and substrate of the semiconductor structure. This stress may be caused based on each transistor-based operation of the semiconductor structure (e.g., programming, reading, and erasing) being performed based on application of a voltage difference across the tunneling oxide material. The stress may cause deterioration of the tunneling oxide, shorting across t