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US-20260129918-A1 - TRANSISTOR STRUCTURE FOR VERTICAL FLASH MEMORY, VERTICAL FLASH MEMORY AND METHOD OF FORMING SAME

US20260129918A1US 20260129918 A1US20260129918 A1US 20260129918A1US-20260129918-A1

Abstract

In one aspect, a transistor structure for a vertical NAND flash memory device is provided. The transistor structure includes a semiconductor channel layer, a first auxiliary layer and a second auxiliary layer arranged on opposite sides of the semiconductor channel layer along a first axis, and each of the first auxiliary layer and the second auxiliary layer comprises a first material having a first relative permittivity greater than 1 and less than 3.9. The transistor structure further includes a first dielectric layer arranged above the semiconductor channel layer, the first auxiliary layer and the first auxiliary layer along a second axis that is perpendicular to the first axis; a charge storage layer arranged on the first dielectric layer; a second dielectric layer arranged on the charge storage layer; and a gate layer arranged on the second dielectric layer.

Inventors

  • Devin Verreck
  • Sana Rachidi
  • Maarten Rosmeulen

Assignees

  • IMEC VZW

Dates

Publication Date
20260507
Application Date
20251104
Priority Date
20241105

Claims (19)

  1. 1 . A transistor structure for a vertical NAND flash memory device, the transistor structure comprising: a semiconductor channel layer; a first auxiliary layer and a second auxiliary layer arranged on opposite sides of the semiconductor channel layer along a first axis, wherein each of the first auxiliary layer and the second auxiliary layer comprises a first material having a first relative permittivity greater than 1.0 and less than 3.9; a first dielectric layer arranged above the semiconductor channel layer, the first auxiliary layer, and the second auxiliary layer, along a second axis perpendicular to the first axis; a charge storage layer arranged on the first dielectric layer; a second dielectric layer arranged on the charge storage layer; and a gate layer arranged on the second dielectric layer.
  2. 2 . The transistor structure according to claim 1 , wherein the first auxiliary layer partially extends into the first dielectric layer along the second axis.
  3. 3 . The transistor structure according to claim 1 , wherein the second auxiliary layer partially extends into the first dielectric layer along the second axis.
  4. 4 . The transistor structure according to claim 1 , wherein the first material is or comprises air.
  5. 5 . The transistor structure according to claim 1 , wherein the first material comprises a porous material.
  6. 6 . The transistor structure according to claim 1 , wherein the first dielectric layer comprises a second material having a second relative permittivity, the second relative permittivity being greater than the first relative permittivity.
  7. 7 . The transistor structure according to claim 1 , wherein a cross section of the semiconductor channel layer in a region below the first dielectric layer has a rectangular, trapezoidal, or triangular shape.
  8. 8 . The transistor structure according to claim 6 , the transistor structure further comprising a first spacer layer arranged between the first auxiliary layer and the semiconductor channel layer along the first axis.
  9. 9 . The transistor structure according to claim 8 , the transistor structure further comprising a second spacer layer arranged between the semiconductor channel layer and the second auxiliary layer along the first axis.
  10. 10 . The transistor structure according to claim 8 , wherein the first spacer layer comprises a third material, the third material having a third relative greater than the first relative permittivity and less than the second relative permittivity.
  11. 11 . The transistor structure according to claim 9 , wherein the second spacer layer comprises a third material, the third material having a third relative greater than the first relative permittivity and less than the second relative permittivity.
  12. 12 . The transistor structure according to claim 10 , wherein the third material comprises silicon dioxide (SiO 2 ).
  13. 13 . A vertical NAND flash memory device comprising one or more transistor structures according to claim 1 .
  14. 14 . The vertical NAND flash memory device according to claim 13 , wherein the first dielectric layer serves as a tunnel dielectric layer.
  15. 15 . The vertical NAND flash memory device according to claim 14 , wherein the charge storage layer serves as a floating gate.
  16. 16 . The vertical NAND flash memory device according to claim 15 , wherein the second dielectric layer serves as a blocking dielectric.
  17. 17 . A method of fabricating a transistor structure for a vertical NAND flash memory, the method comprising: forming a semiconductor channel layer; forming a first auxiliary layer and a second auxiliary layer on opposite sides of the semiconductor channel layer along a first axis, wherein the first auxiliary layer and the second auxiliary layer each comprise a first material having a first relative greater than 1.0 and less than 3.9; forming a first dielectric layer above the semiconductor channel layer, the first auxiliary layer, and the second auxiliary layer along a second axis perpendicular to the first axis; forming a charge storage layer on the first dielectric layer; forming a second dielectric layer on the charge storage layer; and forming a gate layer on the second dielectric layer.
  18. 18 . The transistor structure according to claim 1 , wherein the first auxiliary layer has a first thickness along the second axis, the second auxiliary layer has a second thickness along the second axis, and the semiconductor channel layer has a third thickness along the second axis, wherein the first thickness, the second thickness, and the third thickness are substantially the same.
  19. 19 . The transistor structure according to claim 1 , wherein the first auxiliary layer has a first thickness along the second axis, the second auxiliary layer has a second thickness along the second axis, and the semiconductor channel layer has a third thickness along the second axis, wherein the first thickness and the second thickness are substantially the same, and the third thickness is less than the first thickness and the second thickness.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims foreign priority to European Patent Application No. EP 24210894.2, filed Nov. 5, 2024, the entire content of which is incorporated by reference herein in its entirety. BACKGROUND Field The disclosed technology relates to a transistor structure for a vertical NAND flash memory device, a method of processing the transistor structure, and a vertical NAND flash memory device including one or more of the transistor structures. Description of the Related Technology A flash memory is a type of non-volatile memory that can be electrically programmed and erased. A NAND flash is a special type of flash memory, in which the individual memory cells are connected in series in the form of a NAND gate. A NAND flash with a three-dimensional (3D) architecture, e.g., a NAND flash with memory cells that are arranged vertically, is generally referred to as 3D NAND or vertical NAND. NAND flash memory can store information in a non-volatile way in the form of charge carriers (e.g., electrons and/or holes) in a charge trap layer or in a floating gate that is part of a flash cell transistor. The concentration of stored charge carriers can correspond to the bits of information stored in the memory, and can be read by a resulting threshold voltage shift of the flash cell transistor. Quantum tunneling may be utilized to change the concentration of the charge carriers, thereby writing or erasing information into/from the memory. The dimensions of the flash cells of the vertical NAND flash memories have been scaled down over previous technology generations to increase bit densities. The production technology has transitioned from planar devices to vertical, 3D structures, in which the memory string can include a cylindrical memory hole along which the flash cells are stacked, also called gate-all-around (GAA) strings. These strings can be fabricated by first depositing a stack of alternating layers, followed by etching a memory hole and then filling the memory hole with the memory and channel layers. Such 3D structures allow increasing the bit density by adding more cells to the strings, rather than scaling the cell dimensions. However, the etching process becomes more challenging as the aspect ratio of the memory holes increases, thereby ultimately limiting the number of cells on a string. In the 3D trench cell architecture, the memory operation may be further degraded as the vertical cell pitch is scaled, similar to the degradation observed in GAA structures. Combined with the flat cell geometry, this scaling can lead to poor overall memory performance. SUMMARY OF CERTAIN INVENTIVE ASPECTS It is thus an objective of the disclosed technology to provide a 3D trench NAND flash memory structure with improved performance, and an improved method of forming the memory structure. In particular, the above-mentioned disadvantages may be mitigated. The objective and other advantages are achieved by the embodiments provided in the independent claims. Additional advantageous implementations are further defined in the dependent claims. As described herein, the term “vertical NAND flash memory” refers to a 3D NAND flash memory structure. The disclosed technology is directed to a vertical NAND flash memory having a trench-type channel structure, and not to a GAA structure. According to a first aspect, the disclosed technology relates to a transistor structure for a vertical NAND flash memory device. The transistor structure may comprise a semiconductor channel layer, a first auxiliary layer and a second auxiliary layer arranged on two opposite sides of the semiconductor channel layer along a first axis, wherein each of the first auxiliary layer and the second auxiliary layer comprises a first material having a first relative permittivity, the first relative permittivity being larger than 1 and lower than 3.9. The transistor structure may further comprise a first dielectric layer arranged above the semiconductor channel layer, the first auxiliary layer and the second auxiliary layer, along a second axis that is perpendicular to the first axis. Further, the transistor structure may comprise a charge storage layer arranged on the first dielectric layer, a second dielectric layer arranged on the charge storage layer, and a gate layer arranged on the second dielectric layer. The first auxiliary layer and the second auxiliary layer at both sides of the semiconductor channel layer may generally function as “pockets” having a low relative permittivity, as will be discussed further below. The semiconductor channel may be referred to as a fin, which extends between the two auxiliary layers along the second axis, the fin being sandwiched along the first axis between the two auxiliary layers. Each of the first dielectric material layer and the second dielectric material layer can be formed from a dielectric material, such as silicon oxide or silicon nitride. In this disclosure, the terms “semicondu