US-20260129920-A1 - SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

US20260129920A1US 20260129920 A1US20260129920 A1US 20260129920A1US-20260129920-A1

Abstract

A semiconductor device includes an active area and a junction termination area, each including a drain electrode, a first epitaxial layer of a first conductivity type disposed on the drain electrode, and a second epitaxial layer of the first conductivity type disposed on the first epitaxial layer. The junction termination area further includes a first junction termination area etched on a portion of the second epitaxial layer, and a second junction termination area that is not etched. A field oxide layer is disposed on a portion of the first junction termination area. A doped region of a second conductivity type is disposed to extend from beneath the field oxide layer to the second junction termination area.

Inventors

Young Seo JO
Ji Yong LIM
Ki Hwan Kim

Assignees

MAGNACHIP SEMICONDUCTOR, LTD.

Dates

Publication Date: 20260507
Application Date: 20250918
Priority Date: 20241101

Claims (20)

1 . A semiconductor device comprising: an active area and a junction termination area, each comprising; a drain electrode; a first epitaxial layer of a first conductivity type disposed on the drain electrode; and a second epitaxial layer of the first conductivity type disposed on the first epitaxial layer, wherein the junction termination area further comprises a first junction termination area etched on a portion of the second epitaxial layer, and a second junction termination area that is not etched, wherein a field oxide layer is disposed on a portion of the first junction termination area, and wherein a doped region of a second conductivity type is disposed to extend from beneath the field oxide layer to the second junction termination area.
2 . The semiconductor device of claim 1 , wherein the doped region comprises: a lightly doped region of the second conductivity type disposed in the first junction termination area; and a heavily doped region of the second conductivity type disposed to extend from the first junction termination area to the second junction termination area.
3 . The semiconductor device of claim 2 , wherein a thickness of the heavily doped region is greater than a thickness of the lightly doped region.
4 . The semiconductor device of claim 1 , wherein a surface of the field oxide layer is coplanar with a surface of the second epitaxial layer present in the second junction termination area.
5 . The semiconductor device of claim 1 , further comprising: a body region of the second conductivity type disposed between trench gates in the active area, wherein the body region is connected to the doped region.
6 . The semiconductor device of claim 1 , further comprising: a layer of a second conductivity type formed between the drain electrode and the first epitaxial layer.
7 . The semiconductor device of claim 1 , wherein the junction termination area further comprises: a junction termination etching region disposed between the field oxide layer and the second junction termination area; a field plate insulating layer disposed on inner and outer upper surfaces of the junction termination etching region; a field plate disposed on the field plate insulating layer; an interlayer insulating layer disposed on the field plate; and a source electrode and a gate electrode formed on the interlayer insulating layer.
8 . A semiconductor device comprising: an active area and a junction termination area, each comprising: a drain electrode; a first epitaxial layer of a first conductivity type disposed on the drain electrode; and a second epitaxial layer of the first conductivity type disposed on the first epitaxial layer, wherein the junction termination area further comprises a first junction termination area etched on a portion of the second epitaxial layer, and a second junction termination area that is not etched, wherein a field oxide layer is disposed on a portion of the first junction termination area; and wherein doping regions of a second conductivity type with different thicknesses are disposed in the first junction termination area and the second junction termination area.
9 . The semiconductor device of claim 8 , further comprising: a body region of the second conductivity type formed between trench gates in the active area, wherein the body region is connected to the doped region.
10 . The semiconductor device of claim 8 , wherein the doped regions comprise: a lightly doped region of the second conductivity type disposed on the first junction termination area, and a heavily doped region of the second conductivity type disposed to extend from the first junction termination area to the second junction termination area and having a higher doping concentration than the lightly doped region of the second conductivity type.
11 . The semiconductor device of claim 10 , wherein a thickness of the heavily doped region is greater than a thickness of the lightly doped region.
12 . The semiconductor device of claim 10 , wherein a doping concentration of the lightly doped region gradually decreases toward an edge of the first junction termination area.
13 . The semiconductor device of claim 10 , further comprising: a source electrode electrically contacting the heavily doped region; a field plate disposed on a portion of the heavily doped region and on the lightly doped region; and a gate electrode electrically contacting the field plate.
14 . The semiconductor device of claim 10 , further comprising: a layer of a second conductivity type formed between the drain electrode and the first epitaxial layer.
15 . A method of manufacturing a semiconductor device including an active area and a junction termination area, the method comprising: forming a first epitaxial layer of a first conductivity type on a semiconductor substrate of the first conductivity type; forming a second epitaxial layer of the first conductivity type on the first epitaxial layer; etching an upper surface portion of the second epitaxial layer located in the junction termination area; performing a first ion implantation of a second conductivity type into both etched and unetched junction termination areas to form a first ion implantation region; performing a second ion implantation of the second conductivity type, after the first ion implantation, into a portion of both the etched and unetched junction termination areas to form a second ion implantation region; and forming a field oxide layer on a portion of the etched junction termination area through a thermal oxidation process.
16 . The method of claim 15 , wherein ions implanted during the formation of the field oxide layer are diffused to form a doping region of a second conductivity type.
17 . The method of claim 15 , wherein a mask pattern used during the formation of the first ion implantation region is formed such that spacings between the mask patterns gradually decreases toward a chip edge.
18 . The method of claim 15 , wherein concentrations of ions of the second conductivity type formed during the first ion implantation and the second ion implantation are the same.
19 . The method of claim 15 , further comprising: forming a junction termination etching region after the formation of the field oxide layer; forming a field plate insulating layer in the junction termination etching region; forming a field plate on the field plate insulating layer; forming an interlayer insulating layer on the field plate; and etching a portion of the interlayer insulating layer to form a gate electrode in contact with the field plate and a source electrode in contact with the doping region.
20 . The method of claim 15 , further comprising: performing a grinding process on a bottom surface of the semiconductor substrate; performing an ion implantation process of a second conductivity type, after the grinding process, to form a layer of the second conductivity type; and forming a drain electrode on a bottom surface of the layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit under 35 U.S.C. § 119(a) of Korean Patent Application No. 10-2024-0153615, filed on Nov. 1, 2024, the entire disclosure of which is incorporated herein by reference for all purposes. BACKGROUND 1. Field The present disclosure relates to a semiconductor device capable of achieving a more stable withstand voltage compared to the conventional art, and a method for manufacturing the same. 2. Description of Background Power semiconductor devices, such as MOSFETS (Metal-Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), are primarily used as semiconductor switching devices in power electronics applications. Among these power semiconductor devices, IGBTs can be classified into a horizontal structure, in which a source (or emitter), a gate (or base), and a drain (or collector) electrode are all formed on the upper surface of a semiconductor substrate, and a vertical structure, in which the source and gate electrodes are formed on a top surface of the semiconductor substrate and the drain electrode is formed on a bottom surface of the semiconductor substrate. For IGBT devices, it may be desirable to reduce electric field peaks that occur at the substrate surface in a termination area. The maximum electric field peak typically occurs within a junction termination area where an equipotential ring is present. Under extremely high-current and high-voltage conditions, this region becomes significantly weakened, resulting in avalanche breakdown due to a large leakage current density under reverse bias. To prevent this, techniques such as adopting a P-ring structure by forming a plurality of P-type conductive rings or increasing the area of the junction termination area to reduce the electric field have been proposed. While the P-ring structure can reduce the electric field to a certain extent, it exhibits limitations when applied to high-voltage devices. Alternatively, increasing the junction termination area can further reduce the electric field, but this approach leads to an undesirable increase in device size, thereby presenting another issue. Such IGBT semiconductor devices must be capable of dispersing the electric field generated under reverse bias conditions, thereby reducing the electric field peak and securing a stable breakdown voltage, which is associated with the withstand voltage of the semiconductor device. Therefore, various approaches have been proposed to improve the structure of semiconductor devices in order to enhance withstand voltage performance. The above information is presented as background information only to assist with an understanding of the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above might be applicable as prior art with regard to the disclosure. SUMMARY This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. In one general aspect, a semiconductor device includes an active area and a junction termination area, each including a drain electrode, a first epitaxial layer of a first conductivity type disposed on the drain electrode, and a second epitaxial layer of the first conductivity type disposed on the first epitaxial layer. The junction termination area further includes a first junction termination area etched on a portion of the second epitaxial layer, and a second junction termination area that is not etched. A field oxide layer is disposed on a portion of the first junction termination area. A doped region of a second conductivity type is disposed to extend from beneath the field oxide layer to the second junction termination area. The doped region may include a lightly doped region of the second conductivity type disposed in the first junction termination area, and a heavily doped region of the second conductivity type disposed to extend from the first junction termination area to the second junction termination area. A thickness of the heavily doped region may be greater than a thickness of the lightly doped region. A surface of the field oxide layer may be coplanar with a surface of the second epitaxial layer present in the second junction termination area. The semiconductor device may further include a body region of the second conductivity type formed between trench gates in the active area, wherein the body region is connected to the doped region. The semiconductor device may further include a layer of a second conductivity type formed between the drain electrode and the first epitaxial layer. The junction termination area may further include a junction termination etching region disposed between the field oxide lay