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US-20260129923-A1 - Semiconductor Device and Method of Forming Charge Balanced Power MOSFET Combining Field Plate and Super-Junction

US20260129923A1US 20260129923 A1US20260129923 A1US 20260129923A1US-20260129923-A1

Abstract

A semiconductor device has a substrate and semiconductor layer formed over the substrate. A trench is formed through the semiconductor layer. A polysilicon material is disposed in the trench. A first column of semiconductor material having a first conductivity type extends through the semiconductor layer adjacent to the trench. A second column of semiconductor material having a second conductivity type extends through the semiconductor layer adjacent to the first column of semiconductor material. A conductive layer is formed over the semiconductor layer. The polysilicon material is coupled to the conductive layer and operates as a field plate. A first insulating layer is formed between the polysilicon material and a side surface of the trench. A source region is formed within the semiconductor layer. A gate region is formed adjacent to the insulating layer. A second insulating layer is formed between the gate region and source region.

Inventors

  • Takeshi Ishiguro
  • Aymeric Privat
  • Samuel J. Anderson

Assignees

  • IceMos Technology Limited

Dates

Publication Date
20260507
Application Date
20251230

Claims (20)

  1. 1 . A semiconductor device, comprising: a substrate; a first semiconductor layer formed over the substrate; a second semiconductor layer formed over the first semiconductor layer; a trench formed through the first semiconductor layer and second semiconductor layer and extending to the substrate; a first column of semiconductor material including a first conductivity type and extending through the first semiconductor layer; a second column of semiconductor material including the first conductivity type and extending through the second semiconductor layer over the first column of semiconductor material; a polysilicon material disposed within the trench; an insulating layer formed within the trench; and a gate region disposed over the second semiconductor layer.
  2. 2 . The semiconductor device of claim 1 , wherein the first column of semiconductor material includes a first doping concentration and the second column of semiconductor material includes a second doping concentration greater than the first doping concentration.
  3. 3 . The semiconductor device of claim 1 , wherein a portion of the trench through the first semiconductor layer is absent the polysilicon material.
  4. 4 . The semiconductor device of claim 1 , further including a second column of semiconductor material including a second conductivity type opposite the first conductivity type and disposed within the first semiconductor layer and second semiconductor layer.
  5. 5 . The semiconductor device of claim 4 , further including a body region disposed over the second column of semiconductor material.
  6. 6 . The semiconductor device of claim 5 , further including a source region disposed within the body region.
  7. 7 . A semiconductor device, comprising: a substrate; a first semiconductor layer formed over the substrate; a second semiconductor layer formed over the first semiconductor layer; a trench formed through the first semiconductor layer and second semiconductor layer; a first column of semiconductor material including a first conductivity type and extending through the first semiconductor layer; a second column of semiconductor material including the first conductivity type and extending through the second semiconductor layer; an insulating layer formed within the trench; and a polysilicon material disposed within the trench.
  8. 8 . The semiconductor device of claim 7 , wherein the first column of semiconductor material includes a first doping concentration and the second column of semiconductor material includes a second doping concentration different from the first doping concentration.
  9. 9 . The semiconductor device of claim 7 , wherein a portion of the trench is absent the polysilicon material.
  10. 10 . The semiconductor device of claim 7 , further including a gate region disposed over the second semiconductor layer.
  11. 11 . The semiconductor device of claim 7 , further including a second column of semiconductor material including a second conductivity type opposite the first conductivity type and disposed within the first semiconductor layer and second semiconductor layer.
  12. 12 . The semiconductor device of claim 11 , further including a body region disposed over the second column of semiconductor material.
  13. 13 . The semiconductor device of claim 12 , further including a source region disposed within the body region.
  14. 14 . A method of making a semiconductor device, comprising: providing a substrate; forming a first semiconductor layer over the substrate; forming a second semiconductor layer over the first semiconductor layer; forming a trench through the first semiconductor layer and second semiconductor layer; forming a first column of semiconductor material including a first conductivity type and extending through the first semiconductor layer; forming a second column of semiconductor material including the first conductivity type and extending through the second semiconductor layer; forming an insulating layer formed within the trench; and forming a polysilicon material within the trench.
  15. 15 . The method of claim 14 , wherein the first column of semiconductor material including a first doping concentration and the second column of semiconductor material includes a second doping concentration different from the first doping concentration.
  16. 16 . The method of claim 14 , wherein a portion of the trench is absent the polysilicon material.
  17. 17 . The method of claim 14 , further including forming a gate region over the second semiconductor layer.
  18. 18 . The method of claim 14 , further including forming a second column of semiconductor material including a second conductivity type opposite the first conductivity type within the first semiconductor layer and second semiconductor layer.
  19. 19 . The method of claim 18 , further including forming a body region over the second column of semiconductor material.
  20. 20 . The method of claim 19 , further including forming a source region within the body region.

Description

CLAIM TO DOMESTIC PRIORITY The present application is a continuation of U.S. patent application Ser. No. 17/938,893, filed Oct. 7, 2022, which claims the benefit of U.S. Provisional Application No. 63/264,099, filed Nov. 16, 2021, which application is incorporated herein by reference. U.S. application Ser. No. 17/938,893 further claims the benefit of U.S. Provisional Application No. 63/268,959, filed Mar. 7, 2022, which application is incorporated herein by reference. FIELD OF THE INVENTION The present invention relates in general to a semiconductor device and, more particularly, to a semiconductor device and method of forming a power MOSFET optimized for RDSON and/or COSS. BACKGROUND OF THE INVENTION Semiconductor devices are commonly found in modern electrical products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., a light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, interface circuits, and other signal processing circuits. With respect to the power MOSFET, such devices have been made with a super-junction structure. Advances have been made to merge micro-electrical-mechanical system (MEMS) layer transfer and super-junction technology. Super-junction has been an important development for power devices since the introduction of the insulated gate bipolar transistor (IGBT) in the 1980s. Super-junction has extended the well-known theoretical study on the limit of silicon in high-voltage devices. MEMS super-junction reduces manufacturing cost by merging MEMS processing techniques into CMOS processes to build super-junction metal oxide semiconductor (SJMOS) structures. Super-junction can be challenging to realize in practice, due to the requirement of forming three-dimensional device structures with a high aspect ratio. SJMOS addresses the super-junction manufacturing and cost problem through a low-cost, commercially viable MEMS layer transfer and deep reactive ion etch fabrication technology. The comparison between multiple-epi and the merger of MEMS based SJMOS devices is differentiated by the number of mask layers. There can be twenty or more mask layers used in the manufacture of multi-epi, while SJMOS uses nine mask layers. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electrical devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aerospace, aviation, automotive, data processing centers, industrial controllers, and office equipment. MOSFETs are commonly used in electrical circuits, such as communication systems and power supplies. Power MOSFETs are particularly useful when used as electric switches to enable and disable the conduction of relatively large currents. The on/off state of the power MOSFET is controlled by applying and removing a triggering signal at the gate electrode. When turned on, the electric current in the MOSFET flows between the drain and source. When turned off, the electric current is blocked by the MOSFET. Power MOSFETs are typically arranged in an array of thousands of individual MOSFET cells electrically connected in parallel. The MOSFET cell has an inherent drain-source resistance (RDSON) in the conducting state. The width of the MOSFET cell influences the electrical resistance of the MOSFET cell. The larger the cell width, the larger the resistance. Conversely, the larger the cell density with corresponding smaller cell width, the smaller the resistance. Many applications, such as portable electrical devices, require a low operating voltage, e.g., less than 5 VDC. The low voltage electrical equipment in the portable electrical devices creates a demand for power supplies that can deliver the requisite operating potential. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a block diagram of a power supply and electrical equipment; FIG. 2 is a schematic and block diagram of a pulse width modulated power supply; FIG. 3 illustrates a semiconductor wafer with a plurality of semiconductor die; FIGS. 4a-4an Illustrate a Process of Forming a Multi-cell power MOSFET with a field plate optimized for RDSON; FIGS. 5a-5c illustrate a top view of the multi-cell power MOSFET and field plate; FIGS. 6a-6s illustrate a process of forming a multi-cell power MOSFET optimized for COSS; FIGS. 7a-7b illustrate a top view of the multi-