US-20260129924-A1 - SEMICONDUCTOR DEVICE WITH ISOLATION STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Abstract

A semiconductor device is provided. The semiconductor device includes a first semiconductive region, a second semiconductive region formed in the first semiconductive region and an isolation structure. The isolation structure includes an insulating bottom and a plurality of insulating pillars. The insulating bottom is formed between the first semiconductive region and the second semiconductive region. The plurality of insulating pillars are formed along a peripheral region of the insulating bottom at intervals and extend from the peripheral region of the insulating bottom toward a top of the first semiconductive region, so that the plurality of insulating pillars surround the second semiconductive region formed on the insulating bottom. The first semiconductive region and the second semiconductive region connect with each other through the intervals.

Inventors

• Yu-Wei Tsao
• Kuan-Ju Chen
• Kuan-Yu Chen
• CHING-HSIANG HSIEH
• Chung-Chuan Tseng

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Dates

Publication Date

20260507

Application Date

20241107

Claims (20)

1. 1 . A semiconductor device comprising: a first semiconductive region; a second semiconductive region formed in the first semiconductive region; and an isolation structure comprising: an insulating bottom formed between the first semiconductive region and the second semiconductive region; and a plurality of insulating pillars formed along a peripheral region of the insulating bottom at intervals and extending from the peripheral region of the insulating bottom toward a top of the first semiconductive region, so that the plurality of insulating pillars surround the second semiconductive region formed on the insulating bottom, wherein the first semiconductive region and the second semiconductive region connect with each other through the intervals.
2. 2 . The semiconductor device of claim 1 , wherein each of the plurality of insulating pillars has a trapezoid top cross section having a baseline and a topline, and wherein the baseline or the topline of each of the plurality of insulating pillars abuts the second semiconductive region.
3. 3 . The semiconductor device of claim 2 , wherein a length between the baseline and the topline ranges from about 0.5 μm to about 4 μm.
4. 4 . The semiconductor device of claim 1 , wherein the isolation structure further comprises at least one embedded doped region abutting the insulating bottom; and wherein the at least one embedded doped region comprises materials with a high etching selectivity in respect to the first semiconductive region and the second semiconductive region.
5. 5 . The semiconductor device of claim 1 , wherein a thickness of the insulating bottom is decreased from a peripheral edge of the insulating bottom to a central portion of the insulating bottom.
6. 6 . The semiconductor device of claim 1 , wherein the top of the first semiconductive region, a top of the second semiconductive region, and a top of the isolation structure are coplanar with each other.
7. 7 . The semiconductor device of claim 1 , wherein each of the plurality of insulating pillars comprises different insulating materials.
8. 8 . A semiconductor device comprising: a first semiconductive region; a second semiconductive region formed in the first semiconductive region; and an isolation structure comprising: an insulating bottom formed between the first semiconductive region and the second semiconductive region; and a plurality of insulating pillars surrounding the second semiconductive regionformed along a peripheral region of the insulating bottom at intervals and extending from the peripheral region of the insulating bottom toward a top of the first semiconductive region, so that the plurality of insulating pillars surround the second semiconductive region formed on the insulating bottom, wherein a narrowest width of each of the interval between two of the plurality of insulating pillars is greater than 0 μm; and wherein a ratio of the narrowest widths of all of the intervals to a perimeter of the second semiconductive region ranges from about 5% to about 40%.
9. 9 . The semiconductor device of claim 8 , wherein the narrowest width of each of the interval between two of the plurality of insulating pillars ranges from about 0.1 μm to about 3 μm.
10. 10 . The semiconductor device of claim 8 , wherein each of the plurality of insulating pillars has a trapezoid top cross section having a baseline and a topline and the baseline abuts the second semiconductive region.
11. 11 . The semiconductor device of claim 10 , wherein a ratio of the narrowest widths of all of the intervals to total widths of the baseline of all of the plurality of insulating pillars ranges from about 10% to about 50%.
12. 12 . The semiconductor device of claim 10 , wherein a length between the baseline and the topline ranges from about 0.5 μm to about 4 μm.
13. 13 . The semiconductor device of claim 8 , wherein the plurality of insulating pillars surrounding the second semiconductive region have a same shape.
14. 14 . The semiconductor device of claim 8 , wherein the second semiconductive region is a tetrahedron; and the plurality of insulating pillars comprising four L-shape insulating pillars formed at four corners of the second semiconductive region.
15. 15 . The semiconductor device of claim 8 , wherein each of the plurality of insulating pillars has a triangular top cross section, a rectangular top cross section or a polygonal top cross section.
16. 16 . A method for manufacturing a semiconductor device, comprising: forming an embedded doped region in a substrate; etching the substrate to form a plurality of trenches at intervals surrounding the embedded doped region and etching the embedded doped region to form a lateral tunnel; and filling the plurality of trenches with insulating materials to form a plurality of insulating pillars at the intervals and filling the lateral tunnel with insulating materials to form an insulating bottom, wherein a narrowest width of each of the interval between two of the plurality of insulating pillars is greater than 0 μm.
17. 17 . The method of claim 16 , wherein the embedded doped region is partially retained after the formation of the lateral tunnel.
18. 18 . The method of claim 16 , wherein after the formation of the plurality of insulating pillars and the insulating bottom, the substrate and the plurality of insulating pillars are planarized.
19. 19 . The method of claim 16 , wherein the plurality of trenches are formed by dry etching the substrate and the lateral tunnel is formed by wet etching the embedded doped region.
20. 20 . The method of claim 16 , wherein the embedded doped region has a high etching selectivity in respect to the substrate.

Description

BACKGROUND Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones, and others. Semiconductor devices comprise integrated circuits that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits. Integrated circuits include field-effect transistors (FETs) such as metal oxide semiconductor (MOS) transistors. One of the goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual FETs. Silicon on insulator (SOI) devices have been recognized as one of the possible solutions to enable continued scaling. SOI devices offer a number of advantages over bulk devices. For example, SOI devices exhibit very low junction capacitance compared to bulk devices. The source and drain junction capacitances are almost entirely eliminated. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a perspective view of a semiconductor device, in accordance with some embodiments of the present disclosure. FIG. 2 illustrates a top view of the semiconductor device shown in FIG. 1, in accordance with some embodiments of the present disclosure. FIG. 3A illustrates a cross-sectional side view, which is along line A-A of the semiconductor device shown in FIGS. 1 and 2, in accordance with some embodiments of the present disclosure. FIG. 3B illustrates a cross-sectional side view in accordance with some another embodiments of the present disclosure. FIG. 4 illustrates a perspective view of a semiconductor device, in accordance with some another embodiments of the present disclosure. FIG. 5 illustrates a top view of the semiconductor device shown in FIG. 4, in accordance with some another embodiments of the present disclosure. FIG. 6A to 6F illustrate top views of the semiconductor device in accordance with various embodiments of the present disclosure. FIG. 7A illustrates a top view of the semiconductor device in accordance with some another embodiments of the present disclosure. FIG. 7B a cross-sectional side view along line B-B of the semiconductor device shown in FIG. 7A, in accordance with some embodiments of the present disclosure. FIG. 8 illustrates a top view of the semiconductor device in accordance with some alternative embodiments of the present disclosure. FIG. 9 is a flowchart of a method for forming the semiconductor device in accordance with some embodiments. FIGS. 10A to 10D illustrate various perspective views of forming the semiconductor device in accordance with some embodiments as described in FIG. 9. FIGS. 11A to 11D illustrate various cross-sectional side views along line C-C of the semiconductor device shown in FIGS. 10A to 10D, respectively, in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE DISCLOSURE The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 100 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or