US-20260129925-A1 - SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

US20260129925A1US 20260129925 A1US20260129925 A1US 20260129925A1US-20260129925-A1

Abstract

A semiconductor structure includes a metal gate structure and an isolation structure adjacent to the metal gate structure. The isolation structure includes a first dielectric layer, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer. The first dielectric layer includes carbon of a first concentration, the second dielectric layer includes carbon of a second concentration, and the third dielectric layer includes carbon of a third concentration. The third concentration is greater than the second concentration, and the second concentration is greater than the first concentration.

Inventors

Chia-Hao Chang
Kuo-Cheng Chiang
Chih-Hao Wang
I-Han HUANG

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Dates

Publication Date: 20260507
Application Date: 20241107

Claims (20)

1 . A semiconductor structure comprising: a first metal gate structure and a second metal gate structure extending in a first direction; and an isolation structure disposed between the first metal gate structure and the second metal gate structure, and extending in a second direction different from the first direction, wherein the isolation structure comprises: a first dielectric layer; a second dielectric layer over the first dielectric layer; and a third dielectric layer over the second dielectric layer, wherein a material of the first dielectric layer, a material of the second dielectric layer and a material of the third dielectric layer are different from each other.
2 . The semiconductor structure of claim 1 , further comprising: a first source/drain structure disposed at two sides of the first metal gate structure; and a second source/drain structure disposed at two sides of the second metal gate structure, wherein the first source/drain structure and the second source/drain structure extend in the second direction.
3 . The semiconductor structure of claim 2 , wherein the isolation structure is disposed between the first source/drain structure and the second source/drain structure.
4 . The semiconductor structure of claim 2 , further comprising: a first connecting structure disposed over the first source/drain structure; and a second connecting structure disposed over the second source/drain structure, wherein the isolation structure is disposed between the first connecting structure and the second connecting structure.
5 . The semiconductor structure of claim 1 , wherein a thickness of the third dielectric layer is greater than a thickness of the first dielectric layer.
6 . The semiconductor structure of claim 1 , wherein a thickness of the third dielectric layer is greater than a thickness of the second dielectric layer.
7 . The semiconductor structure of claim 1 , wherein the first dielectric layer comprises a silicon nitride layer, and the second dielectric layer comprises a silicon oxide layer.
8 . The semiconductor structure of claim 1 , wherein the third dielectric layer comprise a dielectric material with dopants.
9 . A method for forming a semiconductor structure, comprising: forming at least a gate structure extending in a first direction over a substrate; removing a portion of the gate structure to form a trench extending in a second direction different from the first direction; conformally forming a first dielectric layer in the trench; conformally forming a second dielectric layer over the first dielectric layer in the trench; forming a third dielectric layer over the second dielectric layer to fill the trench; and removing superfluous potions of the first dielectric layer, the second dielectric layer and the third dielectric layer to form a substantially flat surface, wherein a material of the first dielectric layer, a material of the second dielectric layer and a material of the third dielectric layer are different from each other.
10 . The method of claim 9 , wherein a thickness of the third dielectric layer is greater than a thickness of the first dielectric layer.
11 . The method of claim 9 , wherein a thickness of the third dielectric layer is greater than a thickness of the second dielectric layer.
12 . The method of claim 9 , wherein the first dielectric layer comprises a silicon nitride layer.
13 . The method of claim 9 , wherein the second dielectric layer comprises a silicon oxide layer.
14 . A method for forming a semiconductor structure, comprising: forming at least a sacrificial gate structure extending in a first direction; forming an epitaxial source/drain structure at two sides of the sacrificial gate structure; forming a dielectric structure surrounding the sacrificial gate structure and the epitaxial source/drain structure; replacing the sacrificial gate structure with a metal gate structure; removing a portion of the metal gate structure to form a trench extending in a second direction different from the first direction; forming a multi-layered isolation structure in the trench; and forming a connecting structure coupled to the epitaxial source/drain structure, wherein the multi-layered isolation structure comprises a first dielectric layer, a second dielectric layer and a third dielectric layer, and wherein a material of the first dielectric layer, a material of the second dielectric layer, and a material of the third dielectric layer are different from each other.
15 . The method of claim 14 , wherein a top surface of the multi-layered isolation structure is flush with a top surface of the dielectric structure.
16 . The method of claim 14 , further comprising forming an insulating layer covering the dielectric structure and the multi-layered isolation structure.
17 . The method of claim 14 , wherein the forming of the multi-layered isolation structure comprises: conformally forming a first dielectric layer in the trench; conformally forming a second dielectric layer over the first dielectric layer in the trench; forming a third dielectric layer over the second dielectric layer to fill the trench; and removing superfluous portions of the first dielectric layer, the second dielectric layer and the third dielectric layer to form a substantially flat surface, wherein a material of the first dielectric layer, a material of the second dielectric layer and a material of the third dielectric layer are different from each other.
18 . The method of claim 17 , wherein a thickness of the third dielectric layer is greater than a thickness of the first dielectric layer, and greater than a thickness of the second dielectric layer.
19 . The method of claim 17 , wherein the first dielectric layer comprises a silicon nitride layer, and the second dielectric layer comprises a silicon oxide layer.
20 . The method of claim 14 , wherein the forming of the connecting structure comprises: removing a portion of the dielectric structure and a portion of the multi-layered structure to form a recess exposing a portion of the epitaxial source/drain structure; forming a metal silicide structure over the portion of the epitaxial source/drain structure; and forming the connecting structure in the recess.

Description

BACKGROUND The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices that are able to support greater numbers of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and reducing associated costs. However, such downscaling has also introduced increased complexity to the semiconductor manufacturing process. As technology nodes achieve progressively smaller scales, in some IC designs, researchers have hoped to replace a typical polysilicon gate with a metal gate to improve device performance by decreasing the feature sizes. One approach to forming the metal gate is called a “gate-last” approach, sometimes referred to as a replacement polysilicon gate (RPG) approach. In the RPG approach, the metal gate is fabricated last, which allows for a reduced number of subsequent operations. Further, as dimensions of a transistor decrease, a thickness of a gate dielectric layer may be reduced to maintain performance with a decreased gate length. In order to reduce gate leakage, a high dielectric constant (high-k or HK) gate dielectric layer is used to provide a performance comparable to that provided by a typical gate oxide used in larger technology nodes. A high-k metal gate (HKMG) approach including a metal gate electrode and the high-k gate dielectric layer is therefore recognized. However, the HKMG approach is a complicated approach, and many issues arise. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A is a perspective view illustrating portions of a semiconductor structure in accordance with aspects of the present disclosure in one or more embodiments. FIG. 1B is a cross-sectional view of the semiconductor structure in accordance with aspects of the present disclosure in one or more embodiments. FIG. 1C is a cross-sectional view of the semiconductor structure e in accordance with aspects of the present disclosure in other embodiments. FIG. 2 is a top view of a semiconductor structure in accordance with aspects of the present disclosure in one or more embodiments. FIGS. 3A and 3B are cross-sectional views of a portion of the semiconductor structure taken along a line A-A′ of FIG. 2 in accordance with aspects of the present disclosure in various embodiments. FIG. 4 is an enlarged view of FIG. 3A and FIG. 3B in accordance with aspects of the present disclosure in one or more embodiments. FIG. 5 is a flowchart representing a method for forming a semiconductor structure according to aspects of the present disclosure. FIG. 6 to FIGS. 16A and 16B are schematic drawings at various stages in the method for forming a semiconductor structure according to aspects of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, terms such as “