US-20260129928-A1 - SEMICONDUCTOR DEVICE AND METHODS OF FORMATION

US20260129928A1US 20260129928 A1US20260129928 A1US 20260129928A1US-20260129928-A1

Abstract

Nanostructure channels of a nanostructure transistor are etched during a nanosheet release process for removing sacrificial nanostructure layers between the nanostructure channels. The etching of the nanostructure channels is controlled to increase the efficiency of the etching process such that impurities at central portions of the nanostructure channels are removed. In more detail, parameters such as temperature and/or pressure for etching are controlled to counter the high energy barriers and increase etchant adsorption. As a result, the uniformity in the material removal rates across the nanostructure channels during the etching process is improved so that the nanostructure channels are formed to have a substantially uniform surface profile. The techniques described herein may reduce channel resistance of the nanostructure transistor, which may increase the performance of the nanostructure transistor.

Inventors

Kai-Min Chien
Min-Chia Lee
I-Hsiang MA
Kuo-Chin Liu
Li-Wei Yin
Yih-Ann Lin
Ryan Chia-Jen Chen

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20241101

Claims (20)

1 . A semiconductor device, comprising: a plurality of nanostructure channels arranged in a direction that is approximately perpendicular to a semiconductor substrate of the semiconductor device; a gate structure wrapping around the plurality of nanostructure channels; a first source/drain region adjacent to a first side of the gate structure; and a second source/drain region adjacent to a second side of the gate structure opposing the first side, wherein respective nanostructure channels of the plurality of nanostructure channels adjacent to the gate structure comprise an arc-shaped surface along a direction between the first source/drain region and the second source/drain region.
2 . The semiconductor device of claim 1 , further comprising: a plurality of first inner spacers adjacent to the first source/drain region; and a plurality of second inner spacers adjacent to the second source/drain region, wherein the arc-shaped surface is between a first inner spacer of the plurality of first inner spacers and a second inner spacer of the plurality of second inner spacers opposing the first inner spacer.
3 . The semiconductor device of claim 2 , wherein the arc-shaped surface comprises a first edge contacting the first inner spacer and a second edge contacting the second inner spacer.
4 . The semiconductor device of claim 2 , wherein: the arc-shaped surface comprises a plurality of segments between the first inner spacer and the second inner spacer; and the plurality of segments are angled with respect to each other.
5 . The semiconductor device of claim 1 , wherein: the arc-shaped surface comprises at least two outer segments and a center segment between the at least two outer segments; and the center segment comprises a substantially flat profile.
6 . The semiconductor device of claim 5 , wherein the at least two outer segments and the center segment are configured in a U shape.
7 . The semiconductor device of claim 1 , wherein the arc-shaped surface comprises a concave profile.
8 . The semiconductor device of claim 1 , wherein: the respective nanostructure channels of the plurality of nanostructure channels comprise a first cross-sectional thickness at a central portion and a second cross-sectional thickness at outer portions adjacent to the first source/drain region and the second source/drain region; and the first cross-sectional thickness is less than the second cross-sectional thickness.
9 . The semiconductor device of claim 1 , wherein: the respective nanostructure channels of the plurality of nanostructure channels comprise a central portion having a first cross-sectional thickness and a second cross-sectional thickness; and a difference between the first cross-sectional thickness and the second cross-sectional thickness is less than or equal to approximately 0.2 nanometers.
10 . A semiconductor device, comprising: a plurality of nanostructure channels arranged in a direction that is approximately perpendicular to a semiconductor substrate of the semiconductor device; a gate structure wrapping around the plurality of nanostructure channels, a first source/drain region adjacent to a first side of the gate structure; and a second source/drain region adjacent to a second side of the gate structure opposing the first side, wherein sides of respective portions of the gate structure adjacent to respective nanostructure channels of the plurality of nanostructure channels comprise an arc-shaped surface along a direction between the first source/drain region and the second source/drain region.
11 . The semiconductor device of claim 10 , further comprising: a plurality of first inner spacers between the respective portions of the gate structure and the first source/drain region; and a plurality of second inner spacers between the respective portions of the gate structure and the second source/drain region, wherein the arc-shaped surface is between a first inner spacer of the plurality of first inner spacers and a second inner spacer of the plurality of second inner spacers opposing the first inner spacer.
12 . The semiconductor device of claim 11 , wherein the arc-shaped surface comprises a first edge contacting the first inner spacer and a second edge contacting the second inner spacer.
13 . The semiconductor device of claim 10 , wherein: the respective portions of the gate structure comprise a gate dielectric layer and a metal layer on the gate dielectric layer; and the gate dielectric layer comprises the arc-shaped surface.
14 . The semiconductor device of claim 10 , wherein the arc-shaped surface comprises a convex profile.
15 . The semiconductor device of claim 14 , wherein the arc-shaped surface corresponds to an arc-shaped surface of an adjacent nanostructure channel of the plurality of nanostructure channels comprising a concave profile.
16 . A method, comprising: forming a plurality of nanostructure semiconductor layers and a plurality of sacrificial nanostructure layers such that the plurality of nanostructure semiconductor layers and the plurality of sacrificial nanostructure layers are arranged in an alternating manner in a direction that is approximately perpendicular to a semiconductor substrate of a semiconductor device; performing a first etch operation to etch the plurality of nanostructure semiconductor layers and the plurality of sacrificial nanostructure layers to define a plurality of nanostructure channels that are arranged in the direction that is approximately perpendicular to the semiconductor substrate, wherein the plurality of nanostructure channels and the plurality of sacrificial nanostructure layers are arranged in an alternating manner in the direction that is approximately perpendicular to the semiconductor substrate; performing a second etch operation to etch ends of the plurality of sacrificial nanostructure layers; forming a plurality of inner spacers adjacent to the etched ends of the plurality of sacrificial nanostructure layers; and performing a third etch operation to remove the plurality of sacrificial nanostructure layers from the semiconductor device, wherein the third etch operation results in surfaces of respective nanostructure channels of the plurality of nanostructure channels having a curved concave shape that extends between a first inner spacer of the plurality of inner spacers and a second inner spacer of the plurality of inner spacers opposing the first inner spacer.
17 . The method of claim 16 , wherein performing the third etch operation comprises: performing the third etch operation at a temperature that is greater than or approximately equal to 20 degrees Celsius and less than or approximately equal to 60 degrees Celsius.
18 . The method of claim 16 , wherein performing the third etch operation comprises: performing the third etch operation at a pressure that is greater than or approximately equal to 0.2 Torr and less than or approximately equal to 2 Torr.
19 . The method of claim 16 , wherein performing the third etch operation comprises: performing the third etch operation using a fluorine-based etchant, wherein the fluorine-based etchant removes material from the plurality of nanostructure channels during the third etch operation.
20 . The method of claim 16 , wherein performing the third etch operation comprises: performing the third etch operation using a hydrofluoric acid etchant, wherein the hydrofluoric acid etchant removes material from the plurality of sacrificial nanostructure layers during the third etch operation.

Description

BACKGROUND As semiconductor device manufacturing advances and technology processing nodes decrease in size, transistors may become affected by short channel effects (SCEs) such as hot carrier degradation, barrier lowering, and quantum confinement, among other examples. In addition, as the gate length of a transistor is reduced for smaller technology nodes, source/drain (S/D) electron tunneling increases, which increases the off current for the transistor (the current that flows through the channel of the transistor when the transistor is in an off configuration). Silicon (Si)/silicon germanium (SiGe) nanostructure transistors such as nanowires, nanosheets, and gate-all-around (GAA) devices are potential candidates to overcome short channel effects at smaller technology nodes. Nanostructure transistors are efficient structures that may experience reduced SCEs and enhanced carrier mobility relative to other types of transistors. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A-1C are diagrams of an example implementation of a fin definition process described herein. FIG. 2 is a diagram of an example dummy gate structure formation process described herein. FIG. 3 is a diagram of an example implementation of a source/drain recess formation process described herein. FIGS. 4A and 4B are diagrams of an example implementation of an inner spacer formation process described herein. FIG. 5 is a diagram of an example implementation of a source/drain region formation process described herein. FIG. 6 is a diagram of an example implementation of an interlayer dielectric formation process described herein. FIGS. 7A-7C are diagrams of an example implementation of a nanosheet release process described herein. FIGS. 8A and 8B are diagrams of an example implementation of a gate formation process described herein. FIG. 9 is a diagram of an example of a semiconductor device described herein. FIG. 10 is a flowchart of an example process associated with forming a semiconductor device described herein. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Some nanostructure transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and/or other types of nanostructure transistors) include inner spacers between a source/drain region and a gate structure. The inner spacers may provide various process and/or performance benefits, such as electrical isolation between the source/drain region and the gate structure, and/or protections of the source/drain region from being etched during a replacement gate operation to replace sacrificial nanostructure layers with the gate structure. However, the process of removing the sacrificial nanostructure layers between nanostructure channels to create vacancies for the gate structure can be challenging and may result in high levels of impurities in the nanostructure channels. For example, due to high energy barriers to overcome during etching, impurities may persist at certain portions of the nanostructure channels fol