US-20260129929-A1 - SEMICONDUCTOR DEVICE

US20260129929A1US 20260129929 A1US20260129929 A1US 20260129929A1US-20260129929-A1

Abstract

A semiconductor device including an active pattern extending in a first direction, a first plurality of lower nanosheets on the active pattern, a first plurality of upper nanosheets on the first plurality of lower nanosheets, a second plurality of lower nanosheets on the active pattern and spaced apart from the first plurality of lower nanosheets, and a second plurality of upper nanosheets on the second plurality of lower nanosheets. A first central line dividing the first plurality of lower nanosheets in a second direction crossing the first direction is misaligned in a third direction with a second central line dividing the first plurality of upper nanosheets in the second direction, and a third central line dividing the second plurality of lower nanosheets in the second direction is misaligned in the third direction with a fourth central line dividing the second plurality of upper nanosheets in the second direction.

Inventors

Seung Min Song
Nam Hyun LEE

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251015
Priority Date: 20220517

Claims (20)

1 . (canceled)
2 . A semiconductor device comprising: an active pattern extending in a first direction; a first plurality of lower nanosheets on the active pattern; a first plurality of upper nanosheets on the first plurality of lower nanosheets; a second plurality of lower nanosheets on the active pattern, the second plurality of lower nanosheets spaced apart from the first plurality of lower nanosheets in the first direction; and a second plurality of upper nanosheets on the second plurality of lower nanosheets, wherein a first central line dividing the first plurality of lower nanosheets in a second direction crossing the first direction is misaligned in a third direction with a second central line dividing the first plurality of upper nanosheets in the second direction, the third direction crosses the first direction and the second direction, and a third central line dividing the second plurality of lower nanosheets in the second direction is misaligned in the third direction with a fourth central line dividing the second plurality of upper nanosheets in the second direction.
3 . The semiconductor device of claim 2 , wherein a first sidewall in the second direction of each of the first plurality of lower nanosheets are aligned in the third direction with a first sidewall in the second direction of each of the first plurality of upper nanosheets, and wherein a second sidewall in the second direction of each of the first plurality of lower nanosheets are misaligned in the third direction with a second sidewall in the second direction of each of the first plurality of upper nanosheets.
4 . The semiconductor device of claim 3 , wherein a first sidewall in the second direction of each of the second plurality of lower nanosheets are aligned in the third direction with a first sidewall in the second direction of each of the second plurality of upper nanosheets, and wherein a second sidewall in the second direction of each of the second plurality of lower nanosheets are misaligned in the third direction with a second sidewall in the second direction of each of the second plurality of upper nanosheets.
5 . The semiconductor device of claim 2 , wherein a first sidewall in the second direction of each of the first plurality of lower nanosheets are aligned in the first direction with a first sidewall in the second direction of each of the second plurality of lower nanosheets.
6 . The semiconductor device of claim 5 , wherein a second sidewall in the second direction of each of the first plurality of lower nanosheets are misaligned in the first direction with a second sidewall in the second direction of each of the second plurality of lower nanosheets.
7 . The semiconductor device of claim 5 , wherein a second sidewall in the second direction of each of the first plurality of lower nanosheets are aligned in the first direction with a second sidewall in the second direction of each of the second plurality of lower nanosheets.
8 . The semiconductor device of claim 2 , wherein a first sidewall in the second direction of each of the first plurality of upper nanosheets are aligned in the first direction with a first sidewall in the second direction of each of the second plurality of upper nanosheets, and wherein a second sidewall in the second direction of each of the first plurality of upper nanosheets are misaligned in the first direction with a second sidewall in the second direction of each of the second plurality of upper nanosheets.
9 . The semiconductor device of claim 2 , wherein a first sidewall in the second direction of each of the first plurality of upper nanosheets are misaligned in the first direction with a first sidewall in the second direction of each of the second plurality of upper nanosheets, and wherein a second sidewall in the second direction of each of the first plurality of upper nanosheets are misaligned in the first direction with a second sidewall in the second direction of each of the second plurality of upper nanosheets.
10 . The semiconductor device of claim 2 , wherein the active pattern comprises a first portion disposed under the first plurality of lower nanosheets and a second portion disposed under the second plurality of lower nanosheets, wherein a first sidewall in the second direction of the first portion of the active pattern is aligned in the first direction with a first sidewall in the second direction of the second portion of the active pattern, and wherein a second sidewall in the second direction of the first portion of the active pattern is misaligned in the first direction with a second sidewall in the second direction of the second portion of the active pattern.
11 . The semiconductor device of claim 2 , wherein the active pattern comprises a first portion disposed under the first plurality of lower nanosheets and a second portion disposed under the second plurality of lower nanosheets, wherein a first sidewall in the second direction of the first portion of the active pattern is aligned in the first direction with a first sidewall in the second direction of the second portion of the active pattern, and wherein a second sidewall in the second direction of the first portion of the active pattern is aligned in the first direction with a second sidewall in the second direction of the second portion of the active pattern.
12 . The semiconductor device of claim 2 , further comprising: a first separation layer disposed between the first plurality of lower nanosheets and the first plurality of upper nanosheets; and a second separation layer disposed between the second plurality of lower nanosheets and the second plurality of upper nanosheets, the second separation layer is spaced apart from the first separation layer in the first direction, wherein a width in the second direction of the first separation layer is different from a width in the second direction of the second separation layer.
13 . The semiconductor device of claim 12 , wherein a fifth central line dividing the first separation layer in the second direction is misaligned in the third direction with the first central line dividing the first plurality of lower nanosheets in the second direction, and wherein a sixth central line dividing the second separation layer in the second direction is misaligned in the third direction with the third central line dividing the second plurality of lower nanosheets in the second direction.
14 . The semiconductor device of claim 12 , wherein a fifth central line dividing the first separation layer in the second direction is aligned in the third direction with the second central line dividing the first plurality of upper nanosheets in the second direction, and wherein a sixth central line dividing the second separation layer in the second direction is aligned in the third direction with the fourth central line dividing the second plurality of upper nanosheets in the second direction.
15 . A semiconductor device comprising: an active pattern extending in a first direction; a first plurality of lower nanosheets on the active pattern; a first plurality of upper nanosheets on the first plurality of lower nanosheets; a second plurality of lower nanosheets on the active pattern, the second plurality of lower nanosheets spaced apart from the first plurality of lower nanosheets in the first direction; and a second plurality of upper nanosheets on the second plurality of lower nanosheets, wherein a first sidewall in a second direction crossing the first direction of each of the first plurality of lower nanosheets are aligned in a third direction with a first sidewall in the second direction of each of the first plurality of upper nanosheets, the third direction crosses the first direction and the second direction, wherein a second sidewall in the second direction of each of the first plurality of lower nanosheets are misaligned in the third direction with a second sidewall in the second direction of each of the first plurality of upper nanosheets, wherein a first sidewall in the second direction of each of the second plurality of lower nanosheets are aligned in the third direction with a first sidewall in the second direction of each of the second plurality of upper nanosheets, and wherein a second sidewall in the second direction of each of the second plurality of lower nanosheets are misaligned in the third direction with a second sidewall in the second direction of each of the second plurality of upper nanosheets.
16 . The semiconductor device of claim 15 , wherein a first central line dividing the first plurality of lower nanosheets in the second direction is misaligned in the third direction with a second central line dividing the first plurality of upper nanosheets in the second direction, and wherein a third central line dividing the second plurality of lower nanosheets in the second direction is misaligned in the third direction with a fourth central line dividing the second plurality of upper nanosheets in the second direction.
17 . The semiconductor device of claim 15 , wherein the first sidewall in the second direction of each of the first plurality of upper nanosheets are aligned in the first direction with the first sidewall in the second direction of each of the second plurality of upper nanosheets, and wherein the second sidewall in the second direction of each of the first plurality of upper nanosheets are misaligned in the first direction with the second sidewall in the second direction of each of the second plurality of upper nanosheets.
18 . The semiconductor device of claim 15 , wherein the first sidewall in the second direction of each of the first plurality of upper nanosheets are misaligned in the first direction with the first sidewall in the second direction of each of the second plurality of upper nanosheets, and wherein the second sidewall in the second direction of each of the first plurality of upper nanosheets are misaligned in the first direction with the second sidewall in the second direction of each of the second plurality of upper nanosheets.
19 . The semiconductor device of claim 15 , wherein a width in the second direction of the first plurality of upper nanosheets is different from a width in the second direction of the second plurality of upper nanosheets.
20 . The semiconductor device of claim 15 , wherein a width in the second direction of the first plurality of lower nanosheets is different from a width in the second direction of the second plurality of lower nanosheets.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of U.S. patent application Ser. No. 18/091,603, filed on Dec. 30, 2022, which is based on and claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2022-0060196, filed on May 17, 2022 in the Korean Intellectual Property Office, the contents of which are incorporated by reference herein in their entirety. BACKGROUND 1. Technical Field The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a multi-bridge channel field effect transistor (MBCFETTM). 2. Description of the Related Art Scaling techniques have been proposed for increasing the density of integrated circuit devices. One technique involves the use of a multi-gate transistor. Such a transistor may include a fin or nanowire-shaped silicon body on a substrate. A gate is then formed on a surface of the silicon body. Because a multi-gate transistor uses a three-dimensional (3D) channel, scaling may be achieved. In addition, current controlling capability can be improved without increasing a gate length of the multi-gate transistor. Further, a short channel effect (SCE), in which an electric potential of a channel region is affected by a drain voltage, can be effectively suppressed. SUMMARY Aspects of the present disclosure provide a semiconductor device in which a plurality of upper nanosheets are stacked on a plurality of lower nanosheets and widths between the plurality of lower nanosheets adjacent in a horizontal direction or widths between the plurality of upper nanosheets adjacent in the horizontal direction are different from each other so that integration is improved. According to some embodiments of the present disclosure, there is provided a semiconductor device, comprising a substrate extending a first direction and a second direction perpendicular to the first direction, an active pattern extending in the first direction on the substrate, the active pattern protrudes from the substrate in a third direction perpendicular to the first direction and the second direction, a first plurality of lower nanosheets stacked apart from each other in the third direction on the active pattern, a second plurality of lower nanosheets stacked apart from each other in the third direction on the active pattern, the second plurality of lower nanosheets are spaced apart from the first plurality of lower nanosheets in the first direction, a first plurality of upper nanosheets stacked apart from each other in the third direction on the first plurality of lower nanosheets, the first plurality of upper nanosheets are spaced apart from the first plurality of lower nanosheets in the third direction, a second plurality of upper nanosheets stacked apart from each other in the third direction on the second plurality of lower nanosheets, the second plurality of upper nanosheets are spaced apart from the second plurality of lower nanosheets in the third direction, a first upper gate electrode extending in the second direction on the active pattern, the first upper gate electrode surrounds the first plurality of upper nanosheets, and a second upper gate electrode extending in the second direction on the active pattern, the second upper gate electrode is spaced apart from the first upper gate electrode in the first direction, the second upper gate electrode surrounds the second plurality of upper nanosheets, wherein a width in the second direction of the first plurality of upper nanosheets is different from a width in the second direction of the second plurality of upper nanosheets. According to some embodiments of the present disclosure, there is provided a semiconductor device, comprising a substrate extending a first direction and a second direction perpendicular to the first direction, an active pattern extending in the first direction on the substrate, the active pattern protrudes from the substrate in a third direction perpendicular to the first direction and the second direction, a first plurality of lower nanosheets stacked apart from each other in the third direction on the active pattern, a second plurality of lower nanosheets stacked apart from each other in the third direction on the active pattern, the second plurality of lower nanosheets are spaced apart from the first plurality of lower nanosheets in the first direction, a first plurality of upper nanosheets stacked apart from each other in the third direction on the first plurality of lower nanosheets, the first plurality of upper nanosheets are spaced apart from the first plurality of lower nanosheets in the third direction, and a second plurality of upper nanosheets stacked apart from each other in the third direction on the second plurality of lower nanosheets, the second plurality of upper nanosheets are spaced apart from the second plurality of lower nanosheets in the third direction, wherein a width of the first plurality of lower nanosheets in the second