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US-20260129931-A1 - SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

US20260129931A1US 20260129931 A1US20260129931 A1US 20260129931A1US-20260129931-A1

Abstract

A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure includes: epitaxially growing a semiconductor material among at least two channel layers; implanting pnictogen dopants in the semiconductor material; implanting chalcogen dopants in the semiconductor material; annealing the semiconductor material with the chalcogen dopants; forming a bottom contact etching stop layer (BCESL) on the semiconductor material with the chalcogen dopants; and etching the BCESL and forming a metal layer above the semiconductor material.

Inventors

  • Jui-Lin KUO
  • Jin Cai
  • Wan-Ting KUNG
  • HUANG-LIN CHAO
  • Chih-Hao Wang

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date
20260507
Application Date
20241105

Claims (20)

  1. 1 . A manufacturing method of a semiconductor structure, comprising: epitaxially growing a semiconductor material among at least two channel layers; implanting chalcogen dopants in the semiconductor material; annealing the semiconductor material with the chalcogen dopants; forming a bottom contact etching stop layer (BCESL) on the semiconductor material with the chalcogen dopants; and etching the BCESL and forming a metal layer above the semiconductor material.
  2. 2 . The semiconductor method of the semiconductor structure according to claim 1 , wherein during the step of implanting the chalcogen dopants, a process energy is controlled at 1 to 3 keV.
  3. 3 . The semiconductor method of the semiconductor structure according to claim 1 , wherein during the step of implanting the chalcogen dopants, dose of the chalcogen dopants is controlled at 2e15 to 2e16 cm −2 .
  4. 4 . The semiconductor method of the semiconductor structure according to claim 1 , wherein during the step of implanting the chalcogen dopants, the chalcogen dopants are Selenium (Se) or Tellurium (Te).
  5. 5 . The semiconductor method of the semiconductor structure according to claim 1 , wherein after the step of implanting the chalcogen dopants, a dopant concentration of the chalcogen dopants exceeds 10 21 cm −3 .
  6. 6 . A manufacturing method of a semiconductor structure, comprising: epitaxially growing a semiconductor material among at least two channel layers; implanting pnictogen dopants in the semiconductor material; implanting chalcogen dopants in the semiconductor material; annealing the semiconductor material with the chalcogen dopants; forming a bottom contact etching stop layer (BCESL) on the semiconductor material with the chalcogen dopants; and etching the BCESL and forming a metal layer above the semiconductor material.
  7. 7 . The semiconductor method of the semiconductor structure according to claim 6 , wherein during the step of implanting the chalcogen dopants, a process energy is controlled at 1 to 3 keV.
  8. 8 . The semiconductor method of the semiconductor structure according to claim 6 , wherein during the step of implanting the chalcogen dopants, dose of the chalcogen dopants is controlled at 2e15 to 2e16 cm −2 .
  9. 9 . The semiconductor method of the semiconductor structure according to claim 6 , wherein during the step of implanting the chalcogen dopants, the chalcogen dopants are Selenium (Se) or Tellurium (Te).
  10. 10 . The semiconductor method of the semiconductor structure according to claim 6 , wherein after the step of implanting the chalcogen dopants, a dopant concentration of the chalcogen dopants exceeds 10 21 cm −3 .
  11. 11 . The semiconductor method of the semiconductor structure according to claim 6 , wherein the step of implanting the chalcogen dopants is performed after the step of implanting pnictogen dopants.
  12. 12 . The semiconductor method of the semiconductor structure according to claim 6 , wherein the step of implanting the chalcogen dopants is performed before the step of implanting pnictogen dopants.
  13. 13 . The semiconductor method of the semiconductor structure according to claim 6 , wherein during the step of implanting the pnictogen dopants, a process energy is controlled at 1 to 3 keV.
  14. 14 . The semiconductor method of the semiconductor structure according to claim 6 , wherein during the step of implanting the pnictogen dopants, dose of the pnictogen dopants is controlled at 2e15 to 2e16 cm −2 .
  15. 15 . The semiconductor method of the semiconductor structure according to claim 6 , wherein during the step of implanting the pnictogen dopants, the pnictogen dopants are Phosphorus (P), Arsenic (As) or Antimony (Sb).
  16. 16 . The semiconductor method of the semiconductor structure according to claim 6 , wherein after the step of implanting the pnictogen dopants, a dopant concentration of the pnictogen dopants exceeds 10 21 cm −3 .
  17. 17 . A semiconductor structure, comprising: a substrate; at least two channel layers, disposed above the substrate; a semiconductor material, disposed among the channel layers, wherein the semiconductor material has chalcogen dopants; a bottom contact etching stop layer (BCESL), disposed on the semiconductor material with the chalcogen dopants; and a metal layer, disposed above the semiconductor material.
  18. 18 . The semiconductor structure according to claim 17 , wherein the semiconductor material further has pnictogen dopants.
  19. 19 . The semiconductor structure according to claim 17 , wherein the chalcogen dopants are Selenium (Se) or Tellurium (Te).
  20. 20 . The semiconductor structure according to claim 17 , wherein a dopant concentration of the chalcogen dopants exceeds 10 21 cm −3 .

Description

BACKGROUND The disclosure relates in general to a structure of an electronic element and a manufacturing method thereof, and more particularly to a semiconductor structure and a manufacturing method thereof. Current N-type source-drain implant (pnictogens, e.g., phosphorus and arsenic) suffers from doping limit that carrier concentration does not increase with larger dopant concentration when dopant concentration is larger than 1021 cm−3. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 shows a stereoscopic view of a semiconductor structure 100 according to one embodiment of the present disclosure. FIG. 2 shows the section view of the semiconductor structure 100 along an X-cut section line B-B according to one embodiment of the present disclosure. FIG. 3A shows the relationship between the carrier concentration and the doping concentration for Tellurium (Te), Phosphorus (P), Arsenic (As) and Antimony (Sb) according to one embodiment of the present disclosure. FIG. 3B shows the relationship between the resistivity and the doping concentration for Tellurium (Te), Phosphorus (P), Arsenic (As) and Antimony (Sb) according to one embodiment of the present disclosure. FIG. 4 shows the energy state of the pnictogen dopants according to one embodiment of the present disclosure. FIG. 5 shows the energy state of the chalcogen dopants according to one embodiment of the present disclosure. FIG. 6 illustrates a manufacturing method of a semiconductor structure whose semiconductor material implanted chalcogen dopants instead of pnictogen dopants according to one embodiment of the present disclosure. FIG. 7 shows the atom concentration of the semiconductor material implanted chalcogen dopants instead of pnictogen dopants according to one embodiment of the present disclosure. FIG. 8 shows the carrier density of the semiconductor material implanted chalcogen dopants instead of pnictogen dopants according to one embodiment of the present disclosure. FIG. 9 illustrates a manufacturing method of a semiconductor structure whose semiconductor material implanted both of pnictogen dopants and chalcogen dopants according to one embodiment of the present disclosure. FIG. 10 shows the atom concentration of the semiconductor material implanted both of pnictogen dopants and chalcogen dopants according to one embodiment of the present disclosure. FIG. 11 shows the carrier density of the semiconductor material implanted both of pnictogen dopants and chalcogen dopants according to one embodiment of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. The terms “comprise,” “comprising,” “include,” “including,” “has,” “having,” etc. used in this specification are open-ended and mean “comprises but not limited.” The terms used in this specification generally have their ordinary meanings in the art and in the specific context where each term is used. The use of examples in this specification, including examples of any terms discussed herein, is illustrative only, and in no way limits the scope and meaning of the disclosure or of any exe