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US-20260129932-A1 - SEMICONDUTOR DEVICE AND ELECTRONIC APPARATUS

US20260129932A1US 20260129932 A1US20260129932 A1US 20260129932A1US-20260129932-A1

Abstract

An effective channel width is expanded. A semiconductor device includes: a semiconductor layer having an active region demarcated by a separation region; and a field-effect transistor in which a pair of main electrode regions sandwiching a channel region are provided in the active region and a gate electrode is provided on the channel region. The active region has a first portion extending in one direction in plan view and a second portion extending from the first portion in a direction crossing the one direction, and the channel region is provided across the first portion and the second portion. One of the pair of main electrode regions is provided in the first region in contact with the channel region, and the other is provided in the second region in contact with the channel region, the pair of main electrode regions being positioned on mutually opposite sides sandwiching the channel region.

Inventors

  • Akiko Honjo

Assignees

  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Dates

Publication Date
20260507
Application Date
20260105
Priority Date
20200806

Claims (11)

  1. 1 . A semiconductor device, comprising: a semiconductor layer having an active region demarcated by a separation region; and a field-effect transistor in which a pair of main electrode regions sandwiching a channel region are provided in the active region and a gate electrode is provided on the channel region, the active region having a first portion extending in one direction in plan view and a second portion extending from the first portion in a direction crossing the one direction, the channel region being provided across the first portion and the second portion, one of the pair of main electrode regions being provided in the first region in contact with the channel region, the other being provided in the second region in contact with the channel region, the pair of main electrode regions being positioned on mutually opposite sides sandwiching the channel region.
  2. 2 . The semiconductor device according to claim 1 , further comprising: a first channel boundary portion between the one main electrode region and the channel region; and a second channel boundary portion between the other main electrode region and the channel region, wherein each of the first and second channel boundary portions linearly extends.
  3. 3 . The semiconductor device according to claim 1 , further comprising: a first channel boundary portion between the one main electrode region and the channel region; and a second channel boundary portion between the other main electrode region and the channel region, wherein the first channel boundary portion linearly extends and is orthogonal to an extending direction of the first portion, and the second channel boundary portion linearly extends and is inclined with respect to an extending direction of the second portion.
  4. 4 . The semiconductor device according to claim 1 , further comprising: a first channel boundary portion between the one main electrode region and the channel region; and a second channel boundary portion between the other main electrode region and the channel region, wherein, the first and second channel boundary portions linearly extend parallel to each other.
  5. 5 . The semiconductor device according to claim 1 , wherein a first boundary portion between the one main electrode region and the channel region and a second boundary portion between the other main electrode region and the channel region linearly extend and are inclined at 45 degrees with respect to respective extending directions of the first portion and the second portion in the active region.
  6. 6 . The semiconductor device according to claim 1 , wherein a length of a channel region inner boundary portion between an inner side of the channel region and the separation region and a length of a channel region outer boundary portion between an outer side of the channel region and the separation region are equivalent to each other.
  7. 7 . The semiconductor device according to claim 2 , wherein the gate electrode has a first side crossing the first portion in plan view and a second side that is positioned on a side opposite to the first side and crosses the second portion, the first channel boundary portion is formed by self-alignment with respect to a side of the first side of the gate electrode, and the second channel boundary portion is formed by self-alignment with respect to a side of the second side of the gate electrode.
  8. 8 . The semiconductor device according to claim 1 , wherein a separation region in contact with an inner side of the channel region of the separation region includes a semiconductor region provided in the semiconductor layer.
  9. 9 . The semiconductor device according to claim 1 , wherein the first portion and the second portion of the active region are orthogonal to each other.
  10. 10 . The semiconductor device according to claim 1 , further comprising: a photoelectric conversion device that performs photoelectric conversion; and a readout circuit that reads signal charges photoelectrically converted by the photoelectric conversion device, wherein at least one of a plurality of transistors included in the readout circuit includes the field-effect transistor.
  11. 11 . An electronic apparatus, comprising: a semiconductor device; an optical lens that forms an image of image light from a subject on an imaging surface of the semiconductor device; and a signal processing circuit that performs signal processing on a signal output from the semiconductor device, the semiconductor device including a semiconductor layer having an active region demarcated by a separation region, and a field-effect transistor in which a pair of main electrode regions sandwiching a channel region are provided in the active region and a gate electrode is provided on the channel region, the active region having a first portion extending in one direction in plan view and a second portion extending from the first portion in a direction crossing the one direction, the channel region being provided across the first portion and the second portion, one of the pair of main electrode regions being provided in the first region in contact with the channel region, the other being provided in the second region in contact with the channel region, the pair of main electrode regions being positioned on mutually opposite sides sandwiching the channel region.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 18/007,023, filed Jan. 26, 2023, which is a national stage application under 35 U.S.C. 371 and claims the benefit of PCT Application No. PCT/JP2021/022532, having an international filing date of 14 Jun. 2021, which designated the United States, which PCT application claimed the benefit of Japanese Patent Application No. 2020-134184, filed 6 Aug. 2020, the entire disclosures of each of which are incorporated herein by reference. TECHNICAL FIELD The present technology (technology according to the present disclosure) relates to a semiconductor device and an electronic apparatus, and particularly to a technology effectively applied to a semiconductor device including a field-effect transistor and an electronic apparatus equipped with the semiconductor device. BACKGROUND ART A solid-state imaging device is known as a semiconductor device. This solid-state imaging device is equipped with a readout circuit for reading signal charges photoelectrically converted by a photoelectric conversion device. This readout circuit includes a plurality of transistors such as an amplifier transistor, a selection transistor, and a reset transistor. These transistors are formed in an active region demarcated by a separation region in a semiconductor layer. In recent years, a technology for efficiently disposing transistors by reducing the transistor disposition region (area of the area) accompanying the miniaturization of pixels has been proposed. For example, Patent Literature 1 discloses a layout configuration in which a gate electrode of a transistor is disposed at a corner of an active region formed in an L-shape. CITATION LIST Patent Literature Patent Literature 1: Japanese Patent Application Laid-open No. 2014-022463 DISCLOSURE OF INVENTION Technical Problem Incidentally, as shown in FIG. 3 of Patent Literature 1, in a transistor in which a gate electrode is disposed at a corner of an active region, since a channel region immediately below the gate electrode also has an L-shape, the length at the boundary between the inner side (side inside the corner) of the channel region and the separation region is shorter than the length at the boundary between the outer side (side outside the corner) of the channel region and the separation region. Meanwhile, a current tends to flow through a path in which the distance between a source region and a drain region is minimized. For this reason, the current tends to concentrate inside the channel region and the effective channel width (W) decreases. When the effective channel width decreases, the properties of a field-effect transistor deteriorate due to a short channel effect, and thus, there is a room for improvement from the viewpoint of reliability. An object of the present technology is to provide a semiconductor device and an electronic apparatus that are capable of increasing the effective channel width (W). Solution to Problem (1) A semiconductor device according to an aspect of the present technology includes: a semiconductor layer having an active region demarcated by a separation region; and a field-effect transistor in which a pair of main electrode regions sandwiching a channel region are provided in the active region and a gate electrode is provided on the channel region. Then, the active region has a first portion extending in one direction in plan view and a second portion extending from the first portion in a direction crossing the one direction, and the channel region is provided across the first portion and the second portion. Then, one of the pair of main electrode regions is provided in the first region in contact with the channel region, and the other is provided in the second region in contact with the channel region, the pair of main electrode regions being positioned on mutually opposite sides sandwiching the channel region.(2) An electronic apparatus according to another aspect of the present technology includes: the semiconductor device according to (1) above; an optical lens that forms an image of image light from a subject on an imaging surface of the semiconductor device; and a signal processing circuit that performs signal processing on a signal output from the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic plan view of a main portion showing a configuration example of a semiconductor device according to a first embodiment of the present technology. FIG. 2 is a schematic cross-sectional view showing a cross-sectional structure taken along the line II-II in FIG. 1. FIG. 3 is a schematic cross-sectional view showing a cross-sectional structure taken along the line III-III in FIG. 1. FIG. 4 is a schematic cross-sectional view showing a cross-sectional structure taken along the line IV-IV in FIG. 1. FIG. 5 is a diagram showing a positional relationship between an active region and a gate electrode. FIG. 6 is a diagram showing a