US-20260129934-A1 - METHOD OF MANUFACTURING A REPLACEMENT METAL GATE DEVICE STRUCTURE AND METAL GATE DEVICE STRUCTURE

Abstract

A method of fabricating a semiconductor device includes forming a gate structure over a channel region, wherein the gate structure comprises a gate stack and gate spacers along sidewalls of the gate stack. The method further includes removing the gate stack to expose the channel region. The method further includes depositing a gate dielectric layer over a bottom of the opening. The method further includes forming a doped work function material layer over the gate dielectric layer, wherein the doped work function material layer has a variable dopant concentration, and the doped work function material layer comprises dopants throughout an entirety of the doped work function material layer.

Inventors

• Min Han HSU
• Jung-Chih Tsao

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
• TSMC NANJING COMPANY, LIMITED

Dates

Publication Date

20260507

Application Date

20251230

Priority Date

20200701

Claims (20)

1. 1 . A method of fabricating a semiconductor device, comprising: forming a gate structure over a channel region, wherein the gate structure comprises a gate stack and gate spacers along sidewalls of the gate stack; removing the gate stack to expose the channel region; depositing a gate dielectric layer over a bottom of the opening; and forming a doped work function material layer over the gate dielectric layer, wherein the doped work function material layer has a variable dopant concentration, and the doped work function material layer comprises dopants throughout an entirety of the doped work function material layer.
2. 2 . The method of claim 1 , wherein forming the doped work function material layer comprises forming the doped work function material layer along sidewalls of the gate dielectric layer.
3. 3 . The method of claim 1 , wherein forming the doped work function material layer comprises forming the doped work function material layer having a thickness ranging from about 3 nanometers (nm) to about 9 nm.
4. 4 . The method of claim 1 , wherein forming the doped work function material layer comprises forming the doped work function material layer having a work function value of about 4.7 eV or more.
5. 5 . The method of claim 1 , wherein forming the doped work function material layer comprises forming the doped work function material layer having a work function value of about 4.5 eV or less.
6. 6 . The method of claim 1 , wherein forming the doped work function material layer comprises forming the doped work function material layer including the dopants comprising at least one halide-blocking element.
7. 7 . The method of claim 6 , wherein the at least one halide-blocking element includes one or more of boron, nitrogen, aluminum, silicon, phosphorous, gallium, germanium, arsenic, indium, tin, antimony, titanium, lead, bismuth, or carbon.
8. 8 . The method of claim 6 , wherein the at least one halide-blocking element includes a hydrocarbon.
9. 9 . The method of claim 1 , wherein forming the doped work function material layer comprises forming the doped work function material layer having the variable dopant concentration ranging from about 0.5% by weight to about 5% by weight.
10. 10 . The method of claim 1 , wherein forming the doped work function material comprises forming the doped work function material layer having the variable dopant concentration have a higher dopant concentration as a distance from the gate dielectric increases.
11. 11 . A semiconductor device, comprising: a semiconductor structure; and a gate stack over the semiconductor structure, wherein the gate stack comprises: a gate dielectric layer over a channel region of the semiconductor structure, a work function material layer over the gate dielectric layer, wherein the work function material layer comprises dopants throughout an entirety of the work function material layer, the dopants comprise a hydrocarbon species comprising at least one of CH, CH 2 , or CH 3 , and a concentration of the dopants varies within the work function material layer.
12. 12 . The semiconductor device of claim 11 , wherein the concentration of the dopant increases as a distance from the gate dielectric increases.
13. 13 . The semiconductor device of claim 11 , further comprising a gate electrode layer over the work function material layer.
14. 14 . The semiconductor device of claim 13 , wherein the work function material extends along sidewalls of the gate electrode layer.
15. 15 . The semiconductor device of claim 11 , wherein the gate stack comprises gate spacers, and the gate dielectric layer is between the work function material layer and the gate spacers.
16. 16 . The semiconductor device of claim 11 , further comprising an interfacial layer between the channel region and the gate dielectric layer.
17. 17 . The semiconductor device of claim 11 , wherein the semiconductor structure comprises a semiconductor fin.
18. 18 . A semiconductor device, comprising: a semiconductor structure, wherein the semiconductor structure comprises a channel region; a first source/drain (S/D) region on a first side of the channel region; a second S/D region on a second side of the channel region opposite the first side; and a gate stack over the semiconductor structure, wherein the gate stack comprises: gate spacers; a gate dielectric layer over the channel region, wherein the gate dielectric layer is between the gate spacers, a work function material layer over the gate dielectric layer, wherein the work function material layer comprises dopants throughout an entirety of the work function material layer, the dopants comprise a hydrocarbon species, and a concentration of the dopants varies within the work function material layer.
19. 19 . The semiconductor device of claim 18 , wherein the gate spacers contact the first S/D region and the second S/D region.
20. 20 . The semiconductor device of claim 18 , wherein the concentration of the dopants increases as a proximity to a center of the gate stack increases.

Description

RELATED APPLICATIONS This application is a continuation of U.S. application Ser. No. 17/884,773, filed Aug. 10, 2022, now U.S. Pat. No. 12,512,323, issued Dec. 30, 2025, which is a divisional of U.S. application Ser. No. 17/165,078, filed Feb. 2, 2021, now U.S. Pat. No. 11,769,669, issued Sep. 26, 2023, which claims the priority of China Application No. 202010620909.2, filed Jul. 1, 2020, the contents of which are hereby incorporated by reference in their entireties. BACKGROUND As demands to reduce the dimensions of transistor devices continue, challenges from both fabrication and design issues have resulted in the development of a three-dimensional device architecture, such as a fin-type field effect transistor (FinFET) and the use of a metal gate structure with a high-k gate dielectric material. In some instances, metal gates are manufactured using a replacement metal gate process. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not necessarily to scale. On the contrary, the dimensions and spatial relationship(s) of the various features may be arbitrarily enlarged or reduced for clarity. Like reference numerals denote like features throughout specification and drawings. FIG. 1 is a flowchart of a method of fabricating a semiconductor device, in accordance with some embodiments. FIG. 2 is a cross-sectional view of a semiconductor device after forming a semiconductor fin, isolation structures, and a dummy gate structure over the semiconductor fin, in accordance with some embodiments. FIG. 3 is a cross-sectional view of the semiconductor device of FIG. 2 after forming source/drain regions in the semiconductor fin on opposite sides of a dummy gate stack in the dummy gate structure, in accordance with some embodiments. FIG. 4 is a cross-sectional view of the semiconductor device of FIG. 3 after depositing an inter-layer dielectric (ILD) layer over the source/drain regions and the isolation structures, in accordance with some embodiments. FIG. 5 is a cross-sectional view of the semiconductor device of FIG. 4 after removing the dummy gate stack to forming an opening, in accordance with some embodiments. FIG. 6 is a cross-sectional view of the semiconductor device of FIG. 5 after depositing a gate dielectric layer along sidewalls and bottom of the opening and above the ILD layer, in accordance with some embodiments. FIG. 7 is a cross-sectional view of the semiconductor device of FIG. 6 after depositing a work function material layer over the gate dielectric layer, in accordance with some embodiments. FIG. 8 is a cross-sectional view of the semiconductor device of FIG. 7 after depositing a gate electrode layer over the work function material layer, in accordance with some embodiments. FIG. 9 is a cross-sectional view of the semiconductor device of FIG. 8 after removing excess portions of the gate dielectric layer, the work function material layer, and the gate electrode layer above the ILD layer, in accordance with some embodiments. FIG. 10 is a perspective view of a FinFET, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewis