US-20260129936-A1 - SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

Abstract

A method for forming a semiconductor device structure includes forming fin structures with a stack of alternating first semiconductor layers and second semiconductor layers over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes recessing the first semiconductor layers to form first openings between the second semiconductor layers. The method also includes forming first inner spacers in the first openings. The method also includes removing the fin structures exposed from the gate structure to form a source/drain opening. The method also includes recessing the first semiconductor layers to form second openings between the second semiconductor layers. The method also includes forming second inner spacers in the second openings.

Inventors

• Hong-Chih Chen
• Ta-Chun Lin
• Ming-Heng Tsai
• Zi-Xuan YOU
• Jhon-Jhy Liaw

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20241105

Claims (20)

1. 1 . A method for forming a semiconductor device structure, comprising: forming fin structures with a stack of alternating first semiconductor layers and second semiconductor layers over a substrate; forming a gate structure across the fin structure; recessing the first semiconductor layers to form first openings between the second semiconductor layers; forming first inner spacers in the first openings; removing the fin structures exposed from the gate structure to form a source/drain opening; recessing the first semiconductor layers to form second openings between the second semiconductor layers; and forming second inner spacers in the second openings.
2. 2 . The method for forming the semiconductor device structure as claimed in claim 1 , wherein a top portion of the spacer layer is removed when removing the fin structures exposed from the gate structure.
3. 3 . The method for forming the semiconductor device structure as claimed in claim 1 , wherein a portion of the first inner spacers are exposed from the source/drain opening.
4. 4 . The method for forming the semiconductor device structure as claimed in claim 3 , further comprising: removing the lower first inner spacers exposed from the source/drain opening.
5. 5 . The method for forming the semiconductor device structure as claimed in claim 1 , further comprising: trimming the gate structure after forming the first openings.
6. 6 . The method for forming the semiconductor device structure as claimed in claim 1 , wherein a topmost first opening is wider than a bottommost first openings.
7. 7 . The method for forming the semiconductor device structure as claimed in claim 1 , wherein a dielectric constant of the first inner spacers is less than a dielectric constant of the second inner spacers.
8. 8 . A method for forming a semiconductor device structure, comprising: forming a fin structure with alternating stacked channel layers and sacrificial layers and longitudinally oriented along a first direction over a substrate; forming a dummy gate structure longitudinally oriented along a second direction across the fin structure, wherein the first direction is perpendicular to the second direction; recessing the sacrificial layers in the second direction; depositing a first spacer layer covering the fin structure and the dummy gate structure; etching the fin structure beside the dummy gate structure and the first spacer layer to form first inner spacers covering the sacrificial layers in the second direction recessing the sacrificial layers in the first direction; and forming second inner spacers covering the sacrificial layers in the first direction.
9. 9 . The method for forming the semiconductor device structure as claimed in claim 8 , further comprising: depositing a second spacer layer over the first inner spacers.
10. 10 . The method for forming the semiconductor device structure as claimed in claim 9 , wherein a hardness of the second spacer layer is greater than a hardness of the first spacer layer.
11. 11 . The method for forming the semiconductor device structure as claimed in claim 9 , wherein the second inner spacer layer comprises SiO2, SiCO, SiO2:F, SiN, SiCN, oxide, nitrogen, carbon-based materials, or a combination thereof.
12. 12 . The method for forming the semiconductor device structure as claimed in claim 8 , further comprising: removing the dummy gate structure; removing the sacrificial layers; and forming a gate structure between adjacent spacer layers, adjacent first inner spacers, and adjacent second inner spacers.
13. 13 . The method for forming the semiconductor device structure as claimed in claim 8 , further comprising: forming source/drain epitaxial structures beside the gate structure, wherein the source/drain epitaxial structures are wider than the second inner spacer in the second direction.
14. 14 . A semiconductor device structure, comprising: nanostructures formed over a substrate; source/drain epitaxial structures attached to opposite sides of the nanostructures in a first direction; a gate structure wrapped around the nanostructures and longitudinally oriented along a second direction that is different from the first direction; and first inner spacers and second inner spacers formed between the gate structure and the source/drain epitaxial structures, wherein the first inner spacers cover opposite sidewalls of the second inner spacers in the second direction.
15. 15 . The semiconductor device structure as claimed in claim 14 , wherein a bottommost one of the first inner spacers is narrower than a topmost one of the first inner spacers.
16. 16 . The semiconductor device structure as claimed in claim 14 , wherein the second inner spacers and the first inner spacers have different widths.
17. 17 . The semiconductor device structure as claimed in claim 14 , wherein the first inner spacers are wider than the second inner spacers in the second direction in a top view.
18. 18 . The semiconductor device structure as claimed in claim 14 , wherein a hardness of the first inner spacers is greater than a hardness of the second inner spacers.
19. 19 . The semiconductor device structure as claimed in claim 14 , wherein the gate structure has a tip portion sandwiched between one of the first inner spacers and one of the second inner spacer in the second direction.
20. 20 . The semiconductor device structure as claimed in claim 14 , wherein each of the first inner spacers has a width in a range of about 2 nm to about 5 nm.

Description

BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or ILD structures, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual dies are typically packaged separately, in multi-chip modules, for example, or in other types of packaging. Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the gate-all around transistor (GAA). The GAA device gets its name from the gate structure which can extend around the channel region providing access to the channel on two or four sides. GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes. However, the integration of fabrication of the GAA features around the nanowire can be challenging. While the current methods have been satisfactory in many respects, continued improvements are still needed. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A-1E, 1F, 1G, 1H, 1I, 1J, 1K are perspective representations of various stages of forming a semiconductor device structure, in accordance with some embodiments of the disclosure. FIGS. 1E-1, 1F-1, 1G-1, 1H-1, 1I-1, 1J-1 are enlarged perspective representations of various stages of forming a semiconductor device structure, in accordance with some embodiments of the disclosure. FIG. 2 is an enlarged top view of a semiconductor device structure, in accordance with some embodiments of the disclosure. FIGS. 3A-3C are perspective representations of various stages of forming a semiconductor device structure, in accordance with some embodiments of the disclosure. FIGS. 4A and 4B are perspective representations of various stages of forming a semiconductor device structure, in accordance with some embodiments of the disclosure. FIG. 4A-1 is an enlarged perspective representation of a semiconductor device structure, in accordance with some embodiments of the disclosure. FIGS. 5A, 5B and 5C are perspective representations of various stages of forming a semiconductor device structure, in accordance with some embodiments of the disclosure. FIGS. 5A-1 and 5B-1 is an enlarged perspective representation of a semiconductor device structure, in accordance with some embodiments of the disclosure. FIGS. 6A and 6B are perspective representations of various stages of forming a semiconductor device structure, in accordance with some embodiments of the disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method. The nanostructure transistor (e.g. nanosheet transistor, nanowire transistor, multi-bridge channel, nano-ribbon FET, forksheet structures, gate all around (GAA) transistor structures) described bel