US-20260129937-A1 - SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

US20260129937A1US 20260129937 A1US20260129937 A1US 20260129937A1US-20260129937-A1

Abstract

A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first semiconductor layer, a first source/drain structure in contact with on end of the first semiconductor layer, and a first gate structure wrapping around the first semiconductor layer. The second transistor includes a second semiconductor layer, a second source/drain structure in contact with on end of the second semiconductor layer, and a second gate structure wrapping around the second semiconductor layer. A contact plug electrically connects the first source/drain structure and the second source/drain structure, in which the contact plug comprises a top portion and a bottom portion extending downward from a bottom surface of the top portion. A dual-layer spacer structure is along a sidewall of the top portion of the contact plug. A single-layer spacer structure is along a sidewall of the bottom portion of the contact plug.

Inventors

Wei-Yip Loh
Chun-Hsien Huang
Ting-Hsuan LAI

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20241101

Claims (20)

1 . A semiconductor device, comprising: a first transistor over a substrate and comprising: a first semiconductor layer; a first source/drain structure in contact with on end of the first semiconductor layer; and a first gate structure wrapping around the first semiconductor layer; a second transistor vertically stacked above the first transistor and comprising: a second semiconductor layer; a second source/drain structure in contact with on end of the second semiconductor layer; and a second gate structure wrapping around the second semiconductor layer; a contact plug electrically connecting the first source/drain structure and the second source/drain structure, wherein the contact plug comprises a top portion and a bottom portion extending downward from a bottom surface of the top portion; a dual-layer spacer structure along a sidewall of the top portion of the contact plug; and a single-layer spacer structure along a sidewall of the bottom portion of the contact plug.
2 . The semiconductor device of claim 1 , wherein the dual-layer spacer structure comprises: a first spacer layer; and a second spacer layer between the first spacer layer and the sidewall of the top portion of the contact plug.
3 . The semiconductor device of claim 2 , wherein the second spacer layer and the single-layer spacer structure are made of a same material.
4 . The semiconductor device of claim 2 , wherein the first spacer layer is thicker than the second spacer layer.
5 . The semiconductor device of claim 2 , wherein the first spacer layer is in contact with the bottom surface of the top portion of the contact plug.
6 . The semiconductor device of claim 1 , wherein the dual-layer spacer structure is laterally spaced apart from the single-layer spacer structure.
7 . The semiconductor device of claim 1 , wherein the dual-layer spacer structure is thicker than the single-layer spacer structure.
8 . A semiconductor device, comprising: a first transistor over a substrate; a second transistor vertically stacked above the first transistor; a contact plug electrically connecting a first source/drain structure of the first transistor and a second source/drain structure of the second transistor, the contact plug comprising a top portion and a bottom portion below the top portion, wherein the bottom portion of the contact plug extends into the first source/drain structure; a first spacer structure along a sidewall of the top portion of the contact plug; and a second spacer structure along a sidewall of the bottom portion of the contact plug, wherein the first spacer structure is thicker than the second spacer structure.
9 . The semiconductor device of claim 8 , wherein the first spacer structure comprises more layers than the second spacer structure.
10 . The semiconductor device of claim 8 , wherein the first spacer structure comprises: a first spacer layer; and a second spacer layer between the first spacer layer and the contact plug.
11 . The semiconductor device of claim 8 , wherein the second spacer structure is in contact with the second source/drain structure.
12 . The semiconductor device of claim 8 , further comprising: a first isolation structure laterally surrounding the first source/drain structure; and a second isolation structure over the first isolation structure and laterally surrounding the second source/drain structure, wherein the first spacer structure is between the second isolation structure and the top portion of the contact plug.
13 . The semiconductor device of claim 12 , wherein the second spacer structure is in contact with the first isolation structure and the second isolation structure.
14 . The semiconductor device of claim 8 , further comprising a first silicide layer between the first source/drain structure and the bottom portion of the contact plug, wherein the first silicide layer covers at least a sidewall and a bottom surface of the bottom portion of the contact plug.
15 . The semiconductor device of claim 14 , further comprising a second silicide layer between the second source/drain structure and a bottom surface of the top portion of the contact plug.
16 . A method, comprising: forming a device over a substrate and comprising: a first transistor, wherein a first source/drain structure of the first transistor is covered by a first isolation structure; and a second transistor vertically above the first transistor, wherein a second source/drain structure of the second transistor is covered by a second isolation structure; forming a first opening in the second isolation structure and exposing the second source/drain structure; forming a first spacer layer lining the first opening; after forming the first spacer layer, forming a second opening in the first and second isolation structures and exposing the first source/drain structure; forming a second spacer layer lining the first spacer layer and the second opening; performing an etching process to remove horizontal portions of the first spacer layer and the second spacer layer; and forming a contact plug in the first opening and the second opening.
17 . The method of claim 16 , wherein forming the second opening in the first and second isolation structures comprises: forming a mask layer in the first opening; etching the first and second isolation structures through the mask layer to form the second opening; and removing the mask layer.
18 . The method of claim 16 , wherein the etching process is performed such that a recess is formed in the first source/drain structure.
19 . The method of claim 16 , wherein the etching process is performed to expose the first source/drain structure and the second source/drain structure.
20 . The method of claim 16 , wherein vertical portions of the first spacer layer and the second spacer layer remain on a sidewall of the first opening after the etching process is complete.

Description

BACKGROUND The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. However, since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes. As the semiconductor industry further progresses into technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have led to stacked device structure configurations, such as complementary field effect transistors (C-FET) where an n-type multi-gate transistor and a p-type multi-gate transistor are stacked vertically, one over the other. While existing C-FET structures are generally adequate, they are not satisfactory in all aspects. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a perspective view of a semiconductor device in accordance with some embodiments of the present disclosure. FIGS. 2A to 15 illustrate a method in various stages of forming a semiconductor device in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, “around,” “about,” “approximately,” or “substantially” may generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around,” “about,” “approximately,” or “substantially” can be inferred if not expressly stated. One skilled in the art will realize, however, that the values or ranges recited throughout the description are merely examples, and may be reduced or varied with the down-scaling of the integrated circuits. The gate all around (GAA) transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial