US-20260129938-A1 - METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Abstract

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

Inventors

• Kuo-Cheng Chiang
• CHEN-FENG HSU
• Chao-Ching Cheng
• Tzu-Chiang CHEN
• Tung Ying Lee
• Wei-Sheng Yun
• YU-LIN YANG

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20260102

Claims (20)

1. 1 . A semiconductor device, comprising: a first stack of spaced-apart semiconductor wires extending in a first direction away from a substrate; a second stack of spaced-apart semiconductor wires extending in the first direction away from a substrate; an isolation insulating region disposed in the substrate between the first stack and the second stack along a second direction crossing the first direction, wherein the isolation insulating region comprises an oxide; an epitaxial layer contacting the semiconductor wires as seen in a cross section view along a third direction crossing the first and second directions; a gate structure disposed over the semiconductor wires, wherein the gate structure comprises a gate dielectric layer and gate electrode layer disposed over the gate dielectric layer; a gate sidewall spacer extending in the first direction along a side of the gate electrode layer; and an insulating spacer comprising a different material than the gate sidewall spacer bounded by the gate sidewall spacer, the epitaxial layer, a semiconductor wire, and the gate dielectric layer.
2. 2 . The semiconductor device of claim 1 , wherein the insulating spacer is separated from the gate electrode layer by the gate dielectric layer.
3. 3 . The semiconductor device of claim 1 , wherein the insulating spacer comprises two layers.
4. 4 . The semiconductor device of claim 3 , wherein the two layers are a first layer and a second layer disposed over the first layer, and the first layer has a smaller thickness than the second layer.
5. 5 . The semiconductor device of claim 4 , wherein the first layer of the insulating spacers is in contact with the gate dielectric layer.
6. 6 . The semiconductor device of claim 1 , wherein the insulating spacer comprises at least one of silicon nitride, SiOC, SiOCN, or SiCN.
7. 7 . The semiconductor device of claim 1 , wherein an interface between the gate dielectric layer and the insulating spacer is curved and convex toward the gate dielectric layer.
8. 8 . The semiconductor device of claim 1 , wherein the semiconductor wires comprise SiGe.
9. 9 . A semiconductor device, comprising: a first stack of semiconductor layers extending in a first direction disposed over a substrate; a second stack of semiconductor layers extending in the first direction disposed over the substrate; a shallow trench isolation layer disposed in the substrate between the first and second stack of semiconductor layers along a second direction crossing the first direction; a gate structure comprising a gate electrode layer disposed over a gate dielectric layer wrapping around each of the semiconductor layers, wherein the gate electrode layer comprises titanium; a source/drain epitaxial layer disposed over opposing sides of the gate structure along a third direction crossing the first direction and the second direction; and insulating spacers bounded by the semiconductor layers, the gate dielectric layer and the source/drain epitaxial layer, wherein: the insulating spacers include a first layer comprising an oxide and a second layer disposed over the first layer comprising at least one of a silicon nitride, SiOC, SiOCN, or SiCN.
10. 10 . The semiconductor device of claim 9 , wherein the first layer is in contact with the gate dielectric layer.
11. 11 . The semiconductor device of claim 9 , wherein an interface between the gate dielectric layer and the first layer of the insulating spacers is convex toward the gate dielectric layer.
12. 12 . The semiconductor device of claim 11 , wherein each of the insulating spacers has a triangular cross section.
13. 13 . The semiconductor device of claim 11 , wherein each of the insulating spacers has a semi-circular cross section.
14. 14 . The semiconductor device of claim 9 , wherein a thickness of the second layer is greater than a thickness of the first layer.
15. 15 . The semiconductor device of claim 9 , wherein a bottom of the source/drain epitaxial layer penetrates into a bottom fin structure.
16. 16 . A semiconductor device, comprising: a first stack of spaced-apart semiconductor wires extending in a first direction away from a substrate; a second stack of spaced-apart semiconductor wires extending in the first direction away from a substrate; an isolation insulating region disposed in the substrate between the first stack and the second stack along a second direction crossing the first direction, a gate dielectric layer wrapping around each semiconductor wire; a gate electrode layer wrapping around each gate dielectric layer, wherein a portion of the gate electrode layer and the gate dielectric layer are disposed over the isolation insulating region; an epitaxial layer disposed over opposing sides of the gate electrode layer along a third direction crossing the first direction and the second direction; and a plurality of insulating spacers bounded by adjacent semiconductor wires, the gate dielectric layer, and the epitaxial layer, wherein each of the insulating spacers comprises a germanium oxide.
17. 17 . The semiconductor device of claim 16 , wherein each of the insulating spacers comprises a first layer and a second layer.
18. 18 . The semiconductor device of claim 17 , wherein the first layer comprises the germanium oxide.
19. 19 . The semiconductor device of claim 17 , wherein the second layer comprises at least one of a silicon nitride, SiOC, SiOCN, or SiCN.
20. 20 . The semiconductor device of claim 17 , wherein a thickness of the second layer is greater than a thickness of the second layer.

Description

RELATED APPLICATIONS This application is a continuation of U.S. application Ser. No. 18/141,897 filed May 1, 2023, which is a continuation of U.S. application Ser. No. 17/080,575 filed Oct. 26, 2020, now U.S. Pat. No. 11,677,010, which is a continuation of application Ser. No. 16/837,853 filed Apr. 1, 2020, now U.S. Pat. No. 10,818,777, which is a continuation-in-part of application Ser. No. 15/798,270 filed Oct. 30, 2017, now U.S. Pat. No. 10,714,592, the entire content of each of which is incorporated herein by reference. TECHNICAL FIELD The disclosure relates to method of manufacturing semiconductor integrated circuits, and more particularly to method of manufacturing semiconductor devices including fin field effect transistors (FinFETs) and/or gate-all-around (GAA) FETs, and semiconductor devices. BACKGROUND As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a multi-gate field effect transistor (FET), including a fin FET (Fin FET) and a gate-all-around (GAA) FET. In a Fin FET, a gate electrode is adjacent to three side surfaces of a channel region with a gate dielectric layer interposed therebetween. Because the gate structure surrounds (wraps) the fin on three surfaces, the transistor essentially has three gates controlling the current through the fin or channel region. Unfortunately, the fourth side, the bottom part of the channel is far away from the gate electrode and thus is not under close gate control. In contrast, in a GAA FET, all side surfaces of the channel region are surrounded by the gate electrode, which allows for fuller depletion in the channel region and results in less short-channel effects due to steeper sub-threshold current swing (SS) and smaller drain induced barrier lowering (DIBL). As transistor dimensions are continually scaled down to sub 10-15 nm technology nodes, further improvements of the GAA FET are required. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A-1D show various views of a semiconductor FET device according to an embodiment of the present disclosure. FIG. 1A is a cross sectional view along the X direction (source-drain direction), FIG. 1B is a cross sectional view corresponding to Y1-Y1 of FIG. 1A, FIG. 1C is a cross sectional view corresponding to Y2-Y2 of FIG. 1A and FIG. 1D shows a cross sectional view corresponding to Y3-Y3 of FIG. 1A. FIGS. 2A-2D show various views of a semiconductor FET device according to an embodiment of the present disclosure. FIG. 2A is a cross sectional view along the X direction (source-drain direction), FIG. 2B is a cross sectional view corresponding to Y1-Y1 of FIG. 2A, FIG. 2C is a cross sectional view corresponding to Y2-Y2 of FIG. 2A and FIG. 2D shows a cross sectional view corresponding to Y3-Y3 of FIG. 2A. FIGS. 3A-3D show various views of a semiconductor FET device according to an embodiment of the present disclosure. FIG. 3A is a cross sectional view along the X direction (source-drain direction), FIG. 3B is a cross sectional view corresponding to Y1-Y1 of FIG. 3A, FIG. 3C is a cross sectional view corresponding to Y2-Y2 of FIG. 3A and FIG. 3D shows a cross sectional view corresponding to Y3-Y3 of FIG. 3A. FIGS. 4A-4D show various views of a semiconductor FET device according to an embodiment of the present disclosure. FIG. 4A is a cross sectional view along the X direction (source-drain direction), FIG. 4B is a cross sectional view corresponding to Y1-Y1 of FIG. 4A, FIG. 4C is a cross sectional view corresponding to Y2-Y2 of FIG. 1A and FIG. 4D shows a cross sectional view corresponding to Y3-Y3 of FIG. 4A. FIGS. 5A and 5B show one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIGS. 6A and 6B show one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIGS. 7A and 7B show one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIG. 7A shows a cross sectional view for an n-type GAA FET, and FIG. 7B shows a cross sectional view for a p-type GAA FET. FIGS. 8A, 8B and 8C show one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIG. 8A shows a cross sectional view for an n-type GAA FET, and FIG. 8B shows a cross section