US-20260129939-A1 - LDMOS TRANSISTOR WITH SPLIT GATE FIELD PLATE TAPERED TOWARD DRAIN REGION AND RELATED METHOD

Abstract

An LDMOS transistor includes a semiconductor substrate, a channel gate over the semiconductor substrate, a source region to a first side of the channel gate, and a drain region to a second, opposite side of the channel gate. The LDMOS transistor also includes a split gate field plate over the semiconductor substrate where the split gate field plate has a tapered surface that is thinner toward the drain region. In certain embodiments, the split gate field plate has no lateral overlap with the channel gate and an L-shaped gate dielectric separates the split gate field plate from the channel gate and the semiconductor substrate. The split gate field plate can be shorted to the source region to reduce gate-to-drain region (Miller) parasitic capacitance. The LDMOS transistor split gate field plate can be formed with no additional masks.

Inventors

• Guowei Zhang

Assignees

• GLOBALFOUNDRIES SINGAPORE PTE. LTD.

Dates

Publication Date

20260507

Application Date

20241106

Claims (20)

1. 1 . A laterally-diffused metal-oxide semiconductor (LDMOS) transistor, comprising: a semiconductor substrate; a channel gate over the semiconductor substrate; a source region to a first side of the channel gate; a drain region to a second, opposite side of the channel gate; and a split gate field plate over the semiconductor substrate, wherein the split gate field plate has a tapered surface that is thinner toward the drain region.
2. 2 . The LDMOS transistor of claim 1 , wherein the split gate field plate is spaced apart from the channel gate and has no lateral overlap.
3. 3 . The LDMOS transistor of claim 1 , further comprising an L-shaped gate dielectric separating the split gate field plate from the channel gate and the semiconductor substrate.
4. 4 . The LDMOS transistor of claim 3 , wherein the channel gate includes a polysilicon gate body and a dielectric layer between the polysilicon gate body and the semiconductor substrate, wherein a lower portion of the L-shaped gate dielectric separating the split gate field plate from the semiconductor substrate is thicker than the dielectric layer of the channel gate.
5. 5 . The LDMOS transistor of claim 4 , wherein a lateral distance separating the split gate field plate from the channel gate is identical to a thickness of an upper portion of the L-shaped gate dielectric.
6. 6 . The LDMOS transistor of claim 1 , wherein the channel gate and the split gate field plate each include a polysilicon gate body over a continuous planar surface of the semiconductor substrate.
7. 7 . The LDMOS transistor of claim 1 , further comprising a contact on the split gate field plate, the contact over a drain extension region in the semiconductor substrate between the channel gate and the drain region.
8. 8 . The LDMOS transistor of claim 1 , wherein the split gate field plate is electrically connected to the source region.
9. 9 . The LDMOS transistor of claim 1 , further comprising a silicide blocking layer on the semiconductor substrate between the split gate field plate and the drain region.
10. 10 . The LDMOS transistor of claim 1 , wherein the channel gate and the split gate field plate each include a polysilicon gate body and a dielectric layer between the polysilicon gate body and the semiconductor substrate, and wherein the polysilicon gate body of the channel gate is thicker than the polysilicon gate body of the split gate field plate.
11. 11 . The LDMOS transistor of claim 1 , wherein an upper surface of the split gate field plate is higher than an upper surface of the channel gate.
12. 12 . The LDMOS transistor of claim 11 , further comprising a silicide blocking layer on the semiconductor substrate between the split gate field plate and the drain region.
13. 13 . A laterally-diffused metal-oxide semiconductor (LDMOS) transistor, comprising: a semiconductor substrate; a channel gate in the semiconductor substrate; a source region to a first side of the channel gate; a drain region to a second, opposite side of the channel gate; a split gate field plate over the semiconductor substrate, wherein the split gate field plate is spaced apart from the channel gate, has no lateral overlap with the channel gate and has a tapered surface that is thinner toward the drain region; and an L-shaped gate dielectric separating the split gate field plate from the channel gate and the semiconductor substrate.
14. 14 . The LDMOS transistor of claim 13 , wherein the channel gate includes a polysilicon gate body and a gate dielectric between the polysilicon gate body and the semiconductor substrate, wherein a lower portion of the L-shaped gate dielectric separating the split gate field plate from the semiconductor substrate is thicker than the gate dielectric of the channel gate.
15. 15 . The LDMOS transistor of claim 13 , wherein a lateral distance separating the split gate field plate from the channel gate is identical to a thickness of an upper portion of the L-shaped gate dielectric.
16. 16 . The LDMOS transistor of claim 13 , wherein the split gate field plate is electrically connected to the source region.
17. 17 . The LDMOS transistor of claim 13 , further comprising a silicide blocking layer on the semiconductor substrate between the split gate field plate and the drain region.
18. 18 . The LDMOS transistor of claim 13 , wherein the channel gate and the split gate field plate each include a polysilicon gate body and a gate dielectric layer between the polysilicon gate body and the semiconductor substrate, and wherein the polysilicon gate body of the channel gate is thicker than the polysilicon gate body of the split gate field plate.
19. 19 . The LDMOS transistor of claim 13 , wherein an upper surface of the split gate field plate is higher than an upper surface of the channel gate.
20. 20 . A method, comprising: forming a channel gate including a first polysilicon gate body layer over a first gate dielectric layer over a semiconductor substrate, wherein the first polysilicon gate body layer has an end over the first gate dielectric layer; forming a second gate dielectric layer over the end of the first polysilicon gate body layer, wherein the second gate dielectric layer is thicker than the first gate dielectric layer; forming a second polysilicon gate body layer over the second gate dielectric layer over the end of the first polysilicon gate body layer; forming a split gate field plate from the second polysilicon gate body layer over the second gate dielectric layer over the end of the first polysilicon gate body layer; and forming a source region and a drain region configured for a laterally-diffused metal-oxide semiconductor (LDMOS) transistor in the semiconductor substrate, wherein the split gate field plate has a tapered surface that is thinner toward the drain region.

Description

BACKGROUND The present disclosure relates to transistors, and more specifically, to a laterally diffused metal oxide semiconductor (LDMOS) transistor with a split gate field plate tapered toward a drain region of the transistor, and a related method. Laterally diffused metal oxide semiconductor (LDMOS) transistors are used in, for example, radio frequency (RF) devices. LDMOS transistors include, within a semiconductor substrate such as a fin or a bulk substrate, and for an NFET device, a p-well with a source region therein and an n-well with a drain region therein. A channel gate extends over the p-well and n-well with the channel in the p-well and a drain extension region (also referred to in the art as a drain drift region) in the n-well. One challenge with these devices is continuing to reduce size and improve performance, e.g., with lower on resistance (Rdson) and lower parasitic capacitance. SUMMARY All aspects, examples and features mentioned below can be combined in any technically possible way. An aspect of the disclosure provides a laterally-diffused metal-oxide semiconductor (LDMOS) transistor, comprising: a semiconductor substrate; a channel gate over the semiconductor substrate; a source region to a first side of the channel gate; a drain region to a second, opposite side of the channel gate; and a split gate field plate over the semiconductor substrate, wherein the split gate field plate has a tapered surface that is thinner toward the drain region. An aspect of the disclosure provides a laterally-diffused metal-oxide semiconductor (LDMOS) transistor, comprising: a semiconductor substrate; a channel gate in the semiconductor substrate; a source region to a first side of the channel gate; a drain region to a second, opposite side of the channel gate; a split gate field plate over the semiconductor substrate, wherein the split gate field plate over the semiconductor substrate, wherein the split gate field plate is spaced apart from the channel gate, has no lateral overlap with the channel gate and has a tapered surface that is thinner toward the drain region; and an L-shaped gate dielectric separating the split gate field plate from the channel gate and the semiconductor substrate. An aspect of the disclosure provides a method comprising: forming a channel gate including a first polysilicon gate body layer over a first gate dielectric layer over a semiconductor substrate, wherein the first polysilicon gate body layer has an end over the first gate dielectric layer; forming a second gate dielectric layer over the end of the first polysilicon gate body layer, wherein the second gate dielectric layer is thicker than the first gate dielectric layer; forming a second polysilicon gate body layer over the second gate dielectric layer over the end of the first polysilicon gate body layer; forming a split gate field plate from the second polysilicon gate body layer over the second gate dielectric layer over the end of the first polysilicon gate body layer; and forming a source region and a drain region configured for a laterally-diffused metal-oxide semiconductor (LDMOS) transistor in the semiconductor substrate, wherein the split gate field plate has a tapered surface that is thinner toward the drain region. Two or more aspects described in this disclosure, including those described in this summary section, may be combined to form implementations not specifically described herein. The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features, objects and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS The embodiments of this disclosure will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein: FIGS. 1A-B show cross-sectional views of a preliminary structure according to embodiments of the disclosure; FIGS. 2A-B show cross-sectional views of forming a doping region in a semiconductor substrate, according to embodiments of the disclosure; FIGS. 3A-B show cross-sectional views of forming a dielectric layer and a polysilicon gate body layer, according to embodiments of the disclosure; FIGS. 4A-B show cross-sectional views of forming a channel gate and a split gate field plate, according to embodiments of the disclosure; FIGS. 5A-B show cross-sectional views of forming source/drain regions, according to embodiments of the disclosure; FIGS. 6A-B show cross-sectional views of a laterally diffused metal oxide semiconductor (LDMOS) transistor, according to embodiments of the disclosure; FIG. 7 shows a cross-sectional view of an LDMOS transistor, according to other embodiments of the disclosure; FIG. 8 shows a cross-sectional view of an LDMOS transistor, according to yet other embodiments of the disclosure; FIG. 9 shows an enlarged cross-sectional view of a split gate field plate, according to embodiments of t