US-20260129941-A1 - BACKSIDE CONTACTS

US20260129941A1US 20260129941 A1US20260129941 A1US 20260129941A1US-20260129941-A1

Abstract

A semiconductor structure according to the present disclosure includes a backside metal line and a backside contact structure that includes a bar portion disposed on the backside metal line, a first via extending from the bar portion, a second via extending from the bar portion, and a protrusion disposed between the first via and the second via. The semiconductor structure also includes a first source/drain feature over the first via, a second source/drain feature over the second via, and a gate isolation feature disposed between the first via and the second via. The protrusion extends into the gate isolation feature.

Inventors

Yung-Ting Chang
Jui-Lin Chen
Cheng-Ming Lee
Shih-Chieh Wu

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20250221

Claims (20)

1 . A semiconductor structure, comprising: a backside metal line disposed in a backside insulation layer; a backside contact structure comprising: a bar portion disposed on the backside metal line; a first via extending from the bar portion, a second via extending from the bar portion, and a protrusion disposed between the first via and the second via; a first source/drain feature over the first via; a second source/drain feature over the second via; a gate isolation feature disposed between the first via and the second via; and a silicide feature disposed between the first via and the first source/drain feature, wherein the protrusion extends into the gate isolation feature, wherein an electrical conductivity of the first via is greater than an electricity of the silicide feature.
2 . The semiconductor structure of claim 1 , further comprising: a frontside contact feature disposed over the first source/drain feature and the second source/drain feature, wherein a portion of the frontside contact feature extends between the first source/drain feature and the second source/drain feature to interface the gate isolation feature.
3 . The semiconductor structure of claim 1 , wherein a portion of the bar portion overhangs the backside metal line.
4 . The semiconductor structure of claim 1 , wherein the bar portion, the first via, the second via, and the protrusion of the backside contact structure form an M shape.
5 . The semiconductor structure of claim 1 , further comprising: an isolation feature extending along sidewalls of the first via and sidewalls of the second via, wherein a portion of the isolation feature is spaced apart from the first via by a liner, wherein another portion of the isolation feature interfaces the first via.
6 . The semiconductor structure of claim 5 , wherein the isolation feature is formed of an oxide-based material.
7 . The semiconductor structure of claim 5 , wherein a portion of the bar portion is disposed between the backside insulation layer and the isolation feature.
8 . The semiconductor structure of claim 5 , wherein the backside insulation layer is spaced apart from the isolation feature by a hard mask layer.
9 . The semiconductor structure of claim 8 , wherein a sidewall of the bar portion is spaced apart from the hard mask layer by the liner.
10 . The semiconductor structure of claim 8 , wherein the hard mask layer comprises silicon nitride.
11 . A semiconductor structure, comprising: a backside insulation layer; a backside metal line disposed in the backside insulation layer; a hard mask layer over the backside insulation layer; a backside contact structure disposed over the backside metal line, the backside contact structure comprising: a bar portion disposed in the hard mask layer, a first via extending from the bar portion, a second via extending from the bar portion, and a protrusion disposed between the first via and the second via along a direction; a first source/drain feature disposed over the first via; a second source/drain feature disposed over the second via; a gate isolation feature disposed between the first source/drain feature and the second source/drain feature along the direction; an isolation feature extending along sidewalls of the first via and sidewalls of the second via; a contact etch stop layer (CESL) over the isolation feature; and an interlayer dielectric (ILD) layer over the CESL, wherein the isolation feature comprises an oxide-based material, wherein a composition of the CESL is different from a composition of the ILD layer, wherein the bar portion, the first via, the second via, and the protrusion of the backside contact structure form an M shape.
12 . The semiconductor structure of claim 11 , wherein the protrusion partially extends into the gate isolation feature.
13 . The semiconductor structure of claim 11 , wherein the first via is electrically coupled to the first source/drain feature by way of a first silicide feature, wherein the second via is electrically coupled to the second source/drain feature by way of a second silicide feature.
14 . The semiconductor structure of claim 11 , further comprising: a frontside contact feature disposed over the first source/drain feature and the second source/drain feature, wherein a portion of the frontside contact feature extends between the first source/drain feature and the second source/drain feature along the direction to interface the gate isolation feature.
15 . The semiconductor structure of claim 11 , wherein a portion of the bar portion overhangs the backside metal line.
16 . A method, comprising: providing a precursor structure comprising: a first source/drain feature and a second source/drain feature over a frontside source/drain contact, a first base fin over the first source/drain feature, a second base fin over the second source/drain feature, an isolation feature disposed between the first base fin and the second base fin and extending along sidewalls of the first base fin and the second base fin, and a gate isolation feature disposed between the first base fin and the second base fin; depositing a hard mask layer over the isolation feature, the first base fin and the second base fin; forming a patterned photoresist layer over the hard mask layer; etching the precursor structure and the hard mask layer using the patterned photoresist layer as an etch mask to form a joint backside opening that exposes the isolation feature and the gate isolation feature; depositing a liner over the joint backside opening; after the depositing of the liner, performing an anisotropic etch to expose the first source/drain feature and the second source/drain feature; depositing a metal fill in the joint backside opening; and planarizing the metal fill to expose the hard mask layer and to form a backside joint contact, wherein the isolation feature comprises an oxide-based material, wherein a silicide layer is disposed between the first source/drain feature and the frontside source/drain contact, wherein an electrical conductivity of the frontside source/drain contact is greater than an electrical conductivity of the silicide layer.
17 . The method of claim 16 , wherein the etching of the precursor structure etches silicon at a first rate, etches silicon nitride at a second rate, and etches silicon oxide at a third rate, wherein the first rate is greater than the second rate, wherein the second rate is greater than the third rate.
18 . The method of claim 16 , wherein the backside joint contact is M-shaped.
19 . The method of claim 16 , wherein the hard mask layer comprises silicon nitride.
20 . The method of claim 16 , wherein the etching of the precursor structure forms a recess in the gate isolation feature.

Description

PRIORITY DATA This application claims priority to U.S. Provisional Patent Application Ser. No. 63/715,089, filed Nov. 1, 2024, the entirety of which is incorporated herein by reference. BACKGROUND The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far, these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology. Static random access memory (“SRAM”) generally refers to any memory or storage that can retain stored data only when power is applied. As integrated circuit (IC) technologies progress towards smaller technology nodes, multi-gate structures, such as fin-like field effect transistors (FinFETs) or gate-all-around (GAA) transistors, are integrated into SRAM cells to enhance performance. As dimensions of SRAM cells continue to shrink, the contact structures that functionally interconnect the transistors in SRAM cells present additional challenges in reduction of resistance (R) and capacitance (C). BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a circuit schematic of an SRAM cell according to various aspects of the present disclosure. FIG. 2 is a top view of an SRAM cell, according to various aspects of the present disclosure. FIG. 3 is a fragmentary top view of a frontside interconnect structure of an SRAM quad-cell, according to various aspects of the present disclosure. FIG. 4 is fragmentary cross-sectional view along cross section A-A′ in FIG. 3, according to various aspects of the present disclosure. FIG. 5 is a fragmentary top view of a backside interconnect structure of an SRAM quad-cell, according to various aspects of the present disclosure. FIG. 6 is fragmentary cross-sectional view along cross section B-B′ in FIG. 5, according to various aspects of the present disclosure. FIG. 7 is fragmentary cross-sectional view of a backside joint contact along cross section C-C′ in FIG. 5, according to various aspects of the present disclosure. FIG. 8 includes a flowchart of method 300 for forming the backside joint contact, according to one or more aspects of the present disclosure. FIGS. 9-19 illustrate fragmentary cross-sectional views a precursor structure going through various steps of the method 300 in FIG. 8, according to various aspects of the present disclosure. FIG. 20 illustrates a fragmentary cross-sectional view of a semiconductor structure where a jut portion of a backside joint contact overhangs a backside metal line, according to various aspects of the present disclosure. FIG. 21 illustrates a fragmentary top view of a backside interconnect structure of an SRAM quad-cell having the backside joint contact in FIG. 20, according to various aspects of the present disclosure. FIG. 22 illustrates a fragmentary cross-sectional view of a semiconductor structure where jut portions of a backside joint contact overhang a backside metal line, according to various aspects of the present disclosure. FIG. 23 illustrates a fragmentary top view of a backside interconnect structure of an SRAM quad-cell having the backside joint contact in FIG. 22, according to various aspects of the present disclosure. FIG. 24 illustrates a fragmentary cross-sectional view of a semiconductor structure where the backside joint contact merges with a frontside common contact, according to various aspects of the present disclosure. FIG. 25 illustrates a fragmentary top view of a backside interconnect structure of an SRAM quad-cell having the backside joint contact in FIG. 24, according to various aspects of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the descr