US-20260129943-A1 - SEMICONDUCTOR DEVICE WITH ANTI-OXIDATION LAYER

Abstract

A semiconductor device includes gate electrodes spaced apart from each other on a lower structure in a horizontal direction parallel to an upper surface of the lower structure, an insulating layer between the gate electrodes, and an anti-oxidation layer between each of the gate electrodes and the insulating layer. The anti-oxidation layer includes a metal carbide.

Inventors

• Jingyu Park
• Yeonsu Jeong
• Dae Wee Kong
• Youngsu Noh
• Geumbi Mun
• Mingyo Byeon
• Myung Mo AHN
• ByeongSun Yoo
• Yoonji Lee
• Seongyeop Jeong

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20250519

Priority Date

20241107

Claims (20)

1. 1 . A semiconductor device comprising: gate electrodes spaced apart from each other on a lower structure in a horizontal direction that is parallel to an upper surface of the lower structure; an insulating layer between the gate electrodes; and an anti-oxidation layer between each of the gate electrodes and the insulating layer, wherein the anti-oxidation layer comprises a metal carbide.
2. 2 . The semiconductor device of claim 1 , wherein the gate electrodes comprise a metal.
3. 3 . The semiconductor device of claim 2 , wherein the gate electrodes and the anti-oxidation layer comprise a same metal.
4. 4 . The semiconductor device of claim 1 , wherein the insulating layer comprises an oxide.
5. 5 . The semiconductor device of claim 1 , wherein the gate electrodes comprise molybdenum (Mo), and wherein the anti-oxidation layer comprises molybdenum carbide (MoC x ).
6. 6 . The semiconductor device of claim 1 , wherein the anti-oxidation layer extends between the lower structure and the insulating layer.
7. 7 . The semiconductor device of claim 1 , wherein the anti-oxidation layer comprises: a first layer between each of the gate electrodes and the insulating layer; and a second layer between the first layer and the insulating layer, wherein the first layer comprises the metal carbide, and wherein the second layer comprises carbon.
8. 8 . The semiconductor device of claim 1 , further comprising: semiconductor patterns spaced apart from each other on the lower structure in the horizontal direction, wherein the gate electrodes are between the semiconductor patterns, and wherein the semiconductor patterns and the gate electrodes extend in a vertical direction vertical to the upper surface of the lower structure.
9. 9 . The semiconductor device of claim 8 , further comprising: a gate insulating pattern interposed between each of the semiconductor patterns and each of the gate electrodes, and extending in the vertical direction.
10. 10 . A semiconductor device comprising: a bit line extending on a substrate in a first direction that is parallel to an upper surface of the substrate; vertical semiconductor patterns spaced apart from each other on the bit line in the first direction, and extending in a vertical direction vertical to the upper surface of the substrate; gate electrodes spaced apart from each other between the vertical semiconductor patterns in the first direction, and extending in a second direction parallel to the upper surface of the substrate and crossing the first direction; an insulating layer between the gate electrodes; and an anti-oxidation layer between each of the gate electrodes and the insulating layer, wherein the anti-oxidation layer comprises carbon.
11. 11 . The semiconductor device of claim 10 , wherein the gate electrodes comprise a metal.
12. 12 . The semiconductor device of claim 10 , wherein the anti-oxidation layer comprises metal carbide.
13. 13 . The semiconductor device of claim 10 , wherein the gate electrodes and the anti-oxidation layer comprise a same metal.
14. 14 . The semiconductor device of claim 10 , further comprising a gate insulating pattern interposed between each of the vertical semiconductor patterns and each of the gate electrodes.
15. 15 . The semiconductor device of claim 14 , further comprising a horizontal semiconductor pattern disposed on the bit line between the vertical semiconductor patterns, wherein the horizontal semiconductor pattern extends in the first direction and is coupled with lower portions of the vertical semiconductor patterns, wherein the gate electrodes are on the horizontal semiconductor pattern, and wherein the gate insulating pattern extends between each of the gate electrodes and the horizontal semiconductor pattern.
16. 16 . The semiconductor device of claim 15 , wherein the gate insulating pattern extends between the insulating layer and the horizontal semiconductor pattern.
17. 17 . The semiconductor device of claim 16 , wherein the anti-oxidation layer is interposed between the insulating layer and the gate insulating pattern.
18. 18 . The semiconductor device of claim 14 , further comprising: lower conductive contacts respectively interposed between the vertical semiconductor patterns and the bit line; and a lower insulating layer between the lower conductive contacts, wherein the gate electrodes and the insulating layer are on the lower insulating layer, and wherein the anti-oxidation layer is interposed between the lower insulating layer and the insulating layer.
19. 19 . The semiconductor device of claim 10 , wherein the anti-oxidation layer comprises: a first layer between each of the gate electrodes and the insulating layer; and a second layer between the first layer and the insulating layer, and wherein the first layer comprises metal carbide, and wherein the second layer comprises carbon.
20. 20 . The semiconductor device of claim 10 , wherein the gate electrodes comprise molybdenum (Mo).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0156742, filed on Nov. 7, 2024, the disclosure of which is incorporated by reference in its entirety. BACKGROUND 1. Field The present disclosure relates to semiconductor devices, and more particularly, to a semiconductor device including field effect transistors and a method for manufacturing the same. 2. Description of Related Art A semiconductor device includes an integrated circuit composed of metal-oxide-semiconductor field effect transistors (MOSFETs). As a size and/or a design rule of the semiconductor device are gradually decreasing, scaling down of the MOSFETs is also gradually being accelerated. As the MOSFETs are gradually scaled down, operation characteristics of the semiconductor device may be deteriorated. Accordingly, research on various methods for overcoming limitations that may be caused by high-integration of the semiconductor device and forming the semiconductor device with improved performance is being conducted. SUMMARY The present disclosure provides a semiconductor device including transistors which may have improved electrical characteristics, when to related semiconductor devices, and a method for manufacturing the same. The present disclosure also provides a semiconductor device that may be easily highly-integrated, and a method for manufacturing the same. According to an aspect of the present disclosure, a semiconductor device includes gate electrodes spaced apart from each other on a lower structure in a horizontal direction parallel to an upper surface of the lower structure, an insulating layer between the gate electrodes, and an anti-oxidation layer between each of the gate electrodes and the insulating layer. The anti-oxidation layer includes a metal carbide. According to an aspect of the present disclosure, a semiconductor device includes a bit line extending on a substrate in a first direction parallel to an upper surface of the substrate, a vertical semiconductor patterns spaced apart from each other on the bit line in the first direction, and extending in a vertical direction vertical to the upper surface of the substrate, a gate electrodes spaced apart from each other between the vertical semiconductor patterns in the first direction, and extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, an insulating layer between the gate electrodes, and an anti-oxidation layer between each of the gate electrodes and the insulating layer. The anti-oxidation layer includes carbon. Additional aspects may be set forth in part in the description which follows and, in part, may be apparent from the description, and/or may be learned by practice of the presented embodiments. BRIEF DESCRIPTION OF THE FIGURES The above and other aspects, features, and advantages of certain embodiments of the present disclosure may be more apparent from the following description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a cross-sectional view schematically illustrating a semiconductor device, according to one or more embodiments of the present disclosure; FIG. 2 is an enlarged diagram of part P1 of FIG. 1, according to one or more embodiments of the present disclosure; FIGS. 3 and 4 are cross-sectional views schematically illustrating a method for manufacturing a semiconductor device, according to one or more embodiments of the present disclosure; FIG. 5 is a cross-sectional view schematically illustrating a semiconductor device, according to one or more embodiments of the present disclosure; FIG. 6 is an enlarged diagram of part P2 of FIG. 5, according to one or more embodiments of the present disclosure; FIGS. 7 and 8 are cross-sectional views schematically illustrating a method for manufacturing a semiconductor device, according to one or more embodiments of the present disclosure; FIG. 9 is a block diagram illustrating a semiconductor device, according to one or more embodiments of the present disclosure; FIGS. 10 and 11 are perspective views briefly illustrating a semiconductor device, according to one or more embodiments of the present disclosure; FIG. 12 is a plan view of a semiconductor device, according to one or more embodiments of the present disclosure; FIG. 13 is a cross-sectional view taken along A-A′ of FIG. 12, according to one or more embodiments of the present disclosure; FIG. 14 is a cross-sectional view taken along B-B′ of FIG. 12, according to one or more embodiments of the present disclosure; FIG. 15 is an enlarged diagram of part P3 of FIG. 13, according to one or more embodiments of the present disclosure; FIGS. 16 to 25 are cross-sectional views illustrating a method for manufacturing a semiconductor device, according to one or more embodiments of the present disclosure; FIG. 26 is a plan view of a semiconductor device, according to one or more embodiments of t