US-20260129944-A1 - SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

US20260129944A1US 20260129944 A1US20260129944 A1US 20260129944A1US-20260129944-A1

Abstract

A semiconductor device includes a semiconductor layer and a gate structure on the semiconductor layer. The gate structure includes a multi-stepped gate dielectric on the semiconductor layer and a gate electrode on the multi-stepped gate dielectric. The multi-stepped gate dielectric includes a first gate dielectric segment having a first thickness and a second gate dielectric segment having a second thickness that is less than the first thickness.

Inventors

Hsin-Fu Lin
Chia-Ta Hsieh
Tsung-Hao YEH

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20251231

Claims (20)

1 . A method for manufacturing a semiconductor device, comprising: forming a dielectric film in a semiconductor layer; depositing a first gate dielectric layer on the semiconductor layer and the dielectric film; patterning the first gate dielectric layer to form a first gate dielectric segment on the dielectric film; depositing a second gate dielectric layer on the semiconductor layer, the second gate dielectric layer being connected to the first gate dielectric segment; and patterning the second gate dielectric layer to form a second gate dielectric segment connected to first gate dielectric segment so as to form a multi-stepped gate dielectric on the semiconductor layer and the dielectric film.
2 . The method according to claim 1 , wherein the multi-stepped gate dielectric is formed to include a first gate dielectric portion and a second gate dielectric portion connected to the first gate dielectric portion, the first gate dielectric portion having a flat upper surface, the second gate dielectric portion having a stepped upper surface that includes a flat upper surface portion connected to and flush with the flat upper surface of the first gate dielectric portion, a projection of the dielectric film on an upper surface of the semiconductor layer being connected to a projection of the second gate dielectric portion on the upper surface of the semiconductor layer.
3 . The method according to claim 2 , wherein the first gate dielectric portion overlaps the dielectric film, and the second gate dielectric portion is non-overlapping with the dielectric film and is in contact with the semiconductor layer.
4 . The method according to claim 1 , wherein the first gate dielectric segment has a first thickness, and the second gate dielectric layer has a second thickness that is less than the first thickness.
5 . The method according to claim 2 , further comprising, after forming the dielectric film, forming a drift region in the semiconductor layer so that the dielectric film is disposed in the drift region.
6 . The method according to claim 5 , further comprising, after forming the drift region, forming a well region in the semiconductor layer, the well region being separated from the dielectric film by a portion of the drift region.
7 . The method according to claim 6 , wherein the drift region has a first surface portion and a second surface portion which are located at two opposite sides of the dielectric film; the second surface portion of the drift region is located between the dielectric film and the well region; and the second dielectric portion is disposed on the second surface portion of the drift region.
8 . The method according to claim 7 , further comprising: depositing a third gate dielectric layer on the second surface portion of the drift region and the well region; and patterning the third gate dielectric layer to form a third gate dielectric segment connected to the second gate dielectric segment so as to form the multi-stepped gate dielectric.
9 . The method according to claim 8 , wherein the third gate dielectric layer has a third thickness that is less than the second thickness.
10 . The method according to claim 8 , wherein the third gate dielectric segment includes: a first dielectric part connected to the second gate dielectric segment and disposed on the second surface portion of the drift region; and a second dielectric part connected to the first dielectric part of the third gate dielectric segment and disposed on the well region.
11 . A method for manufacturing a semiconductor device, comprising: forming a dielectric film, a drift region and a well region in a semiconductor layer in a manner such that the dielectric film is separated from the well region by a first portion of the drift region; depositing a first gate dielectric layer on the the dielectric film, the drift region and the well region; patterning the first gate dielectric layer to form a first gate dielectric segment on the dielectric film and the drift region; depositing a second gate dielectric layer on the first portion of the drift region and the well region, the second gate dielectric layer being connected to the first gate dielectric segment; and patterning the second gate dielectric layer to form a second gate dielectric segment connected to the first gate dielectric segment and disposed on the first portion of the drift region so as to form a multi-stepped gate dielectric on the drift region and the dielectric film.
12 . The method according to claim 11 , wherein the multi-stepped gate dielectric is formed on an upper surface of the semiconductor layer, and includes a first gate dielectric portion and a second gate dielectric portion connected to the first gate dielectric portion, the first gate dielectric portion having a flat upper surface, the second gate dielectric portion having a stepped upper surface that includes a flat upper surface portion connected to and flush with the flat upper surface of the first gate dielectric portion, the first gate dielectric portion overlapping the dielectric film, the second gate dielectric portion being non-overlapping with the dielectric film and being in contact with the semiconductor layer.
13 . The method according to claim 11 , wherein the drift region further includes a second portion that is separated from the first portion of the drift region by the dielectric film; and the first gate dielectric segment is formed on the dielectric film and the first portion and the second portion of the drift region.
14 . The method according to claim 11 , further comprising: depositing a third gate dielectric layer on the first portion of the drift region and the well region; and patterning the third gate dielectric layer to form a third gate dielectric segment connected to the second gate dielectric segment and disposed on the first portion of the drift region and the well region.
15 . The method according to claim 12 , wherein the first gate dielectric portion interfaces the dielectric film; and the second gate dielectric portion interfaces the first portion of the drift region and the well region.
16 . A method for manufacturing a semiconductor device, comprising: forming a dielectric film, a drift region and a well region in a semiconductor layer in a manner such that the dielectric film is separated from the well region by a first portion of the drift region; depositing a first gate dielectric layer on the the dielectric film, the drift region and the well region; patterning the first gate dielectric layer to form a first gate dielectric segment on the dielectric film and the drift region; depositing a second gate dielectric layer on the first portion of the drift region and the well region, the second gate dielectric layer being connected to the first gate dielectric segment; patterning the second gate dielectric layer to form a second gate dielectric segment connected to the first gate dielectric segment and disposed on the first portion of the drift region; depositing a third gate dielectric layer on the first portion of the drift region and the well region, the third gate dielectric layer being connected to the second gate dielectric segment; and patterning the third gate dielectric layer to form a third gate dielectric segment connected to the second dielectric segment and separated from the first gate dielectric segment by the second gate dielectric segment so as to form a multi-stepped gate dielectric on the dielectric film, the drift region and the well region.
17 . The method according to claim 16 , wherein the multi-stepped gate dielectric is formed to include a first gate dielectric portion and a second gate dielectric portion connected to the first gate dielectric portion, the first gate dielectric portion having a flat upper surface, the second gate dielectric portion having a stepped upper surface that includes a flat upper surface portion connected to and flush with the flat upper surface of the first gate dielectric portion, the first gate dielectric portion overlapping the dielectric film, the second gate dielectric portion being non-overlapping with the dielectric film and being in contact with the first portion of the drift region and the well region.
18 . The method according to claim 17 , wherein the drift region further includes a second portion that is separated from the first portion of the drift region by the dielectric film; and the first gate dielectric segment is formed on the dielectric film and the first portion and the second portion of the drift region.
19 . The method according to claim 17 , wherein the first gate dielectric segment includes a first gate dielectric part in contact with the dielectric film and a second gate dielectric part in connect with the first portion of the drift region; the first gate dielectric portion includes the first gate dielectric part of the first gate dielectric segment; and the second gate dielectric portion includes the second gate dielectric part of the first gate dielectric segment, the second gate dielectric segment and the third gate dielectric segment.
20 . The method according to claim 16 , wherein the first gate dielectric segment has a first thickness; the second gate dielectric segment has a second thickness that is less than the first thickness; and the third gate dielectric segment has a third thickness that is less than the second thickness, the second gate dielectric segment being connected between the first gate dielectric segment and the third gate dielectric segment.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application is a continuation of U.S. patent application Ser. No. 18/609,581, filed on Mar. 19, 2024, which is a continuation of U.S. patent application Ser. No. 17/400,594 (now U.S. Pat. No. 11,961,890 B2, issued on Apr. 16, 2024), all of which are hereby expressly incorporated by reference into the present application. BACKGROUND In semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), an excess of hot carriers may degrade reliability, induce high leakage current, or cause malfunction of the MOSFETs. Hence, there is a need to solve this problem. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a flow diagram illustrating a method for manufacturing a semiconductor device in accordance with some embodiments. FIGS. 2 to 21 are schematic views illustrating intermediate stages of a method for manufacturing the semiconductor device in accordance with some embodiments as depicted in FIG. 1. FIG. 22 is a simulation diagram illustrating the contour plots of the electric potential distribution and the hot carrier density of a semiconductor device in which a single-layered gate dielectric is provided. FIG. 23 is a simulation diagram illustrating the contour plots of the electric potential distribution and the hot carrier density of a semiconductor device in accordance with some embodiments in which a multi-stepped gate dielectric is provided. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “on,” “over,” “proximate,” “distal,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. The present disclosure is directed to semiconductor devices and methods for manufacturing the same. The semiconductor devices may be, but not limited to, power MOSFETs, which may be bipolar complementary metal-oxide semiconductor (bipolar CMOS) diffusion metal-oxide semiconductor (DMOS) devices (bipolar-CMOS-DMOS (BCD) devices), for example, LDMOS transistors (lateral diffused metal oxide semiconductor field effect transistors) or other suitable transistors/power devices. FIG. 1 is a flow diagram illustrating a method 100 for manufacturing a semiconductor device in accordance with some embodiments. FIGS. 2 to 21 illustrate schematic views of a semiconductor device 1 during various stages of the method 100 shown in FIG. 1. The method 100 and the semiconductor device 1 are collectively described below. However, additional steps can be provided before, after or during the various stages of the method 100, and some of the steps described herein may be replaced by other steps or be eliminated. Similarly, further additional features may be present in the semiconductor device 1, and/or the features present may be replaced or eliminated in additional embodiments. Referring to FIG. 1, the method 100 begins at block 101, where a trench is formed in a semiconductor layer. Referring to the example illustrated in FIG. 2, a trench 11 is formed in a semiconductor layer 10. In some embodiments, the semiconductor layer 10 may include crystalline silicon, polycrystalline silicon, or a combination thereof. Other suitable semiconductor materials are within the contemplated scope of the present disclosur