US-20260129946-A1 - SEMICONDUCTOR STRUCTURE

US20260129946A1US 20260129946 A1US20260129946 A1US 20260129946A1US-20260129946-A1

Abstract

A semiconductor structure includes a substrate and a contact field plate (CFP) on the substrate. The contact field plate includes an insulation layer on the substrate, a poly gate over the insulation layer, a first-type semiconductor doping region in the poly gate; and a second-type semiconductor doping region in the poly gate.

Inventors

Kai-Chun Chang
Yen-Chen Liao
Ming-Chi Fan
Der-Ming Kuo

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20241105

Claims (20)

1 . A semiconductor structure, comprising: a substrate; and a contact field plate (CFP) on the substrate, comprising: an insulation layer on the substrate; a poly gate over the insulation layer; a first-type semiconductor doping region in the poly gate; and a second-type semiconductor doping region in the poly gate.
2 . The semiconductor structure according to claim 1 , wherein the first-type semiconductor doping region has a first length, the second-type semiconductor doping region has a second length, and the second length is equal to the first length.
3 . The semiconductor structure according to claim 1 , wherein the first-type semiconductor doping region comprising a plurality of first sub-regions, and the first sub-regions respectively have different doping concentrations.
4 . The semiconductor structure according to claim 3 , wherein a first one of the first sub-regions is closer to the second-type semiconductor doping region than a second one of the first sub-regions, and the first one of the first sub-regions has a doping concentration less than that of the second one of the first sub-regions.
5 . The semiconductor structure according to claim 4 , wherein the first one of the first sub-regions has a first sub-length equal to that of the second one of the first sub-regions.
6 . The semiconductor structure according to claim 1 , wherein the second-type semiconductor doping region comprising a plurality of second sub-regions, and the second sub-regions respectively have different doping concentrations.
7 . The semiconductor structure according to claim 6 , wherein a first one of the second sub-regions is closer to the first-type semiconductor doping region than a second one of the second sub-regions, and the first one of the second sub-regions has a doping concentration less than that of the second one of the second sub-regions.
8 . The semiconductor structure according to claim 7 , wherein the first one of the second sub-regions has a second sub-length equal to that of the second one of the second sub-regions.
9 . The semiconductor structure according to claim 1 , wherein the first-type semiconductor doping region and the second-type semiconductor doping region are disposed side-by-side.
10 . A semiconductor structure, comprising: a substrate; and a contact field plate on the substrate, comprising: an insulation layer on the substrate; a poly gate over the insulation layer; and a silicide over the poly gate, comprising: a first silicide portion having a first thickness; and a second silicide portion having a second thickness; wherein the first thickness and the second thickness are different.
11 . The semiconductor structure according to claim 10 , further comprising: a NMOS transistor on the substrate; wherein the first silicide portion is closer to the NMOS transistor than the second silicide portion, and the first thickness is greater than the second thickness.
12 . The semiconductor structure according to claim 10 , further comprising: a PMOS transistor on the substrate; wherein the first silicide portion is closer to the PMOS transistor than the second silicide portion, and the first thickness is less than the second thickness.
13 . The semiconductor structure according to claim 10 , wherein the first silicide portion has a first length, the second silicide portion has a second length, and the first length is equal to the second length.
14 . The semiconductor structure according to claim 10 , wherein the silicide further comprises: a third silicide portion having a third thickness; wherein the second silicide portion is disposed between the first silicide portion and the third silicide portion, and the third thickness ranges between the first thickness and the second thickness.
15 . The semiconductor structure according to claim 14 , wherein the first silicide portion has a first length, the second silicide portion has a second length, the third silicide portion has a third length, and the first length, the second length and the third length are equal.
16 . The semiconductor structure according to claim 10 , wherein the first silicide portion and the second silicide portion are disposed side-by-side.
17 . A semiconductor structure, comprising: a substrate comprising a plurality of doping regions, wherein the doping regions have different doping concentrations; and a contact field plate on the substrate and above the doping regions.
18 . The semiconductor structure according to claim 17 , wherein the substrate further comprises a semiconductor well, and the semiconductor structure further comprises: a transistor on the semiconductor well; wherein a first one of the doping regions is located between the semiconductor well and a second one of the doping regions, and the second one has a doping concentration greater than that of the first one.
19 . The semiconductor structure according to claim 17 , wherein the contact field plate has a first length and a second length, the first length overlap the first one of the doping regions, the second length overlap the second one of the doping regions, and the first length is equal to the second length.
20 . The semiconductor structure according to claim 17 , wherein the doping regions are disposed side by side.

Description

BACKGROUND A semiconductor structure includes a transistor and a contact field plate (CFP), wherein the contact field plate may discharge a voltage to a grounding potential for preventing the transistor from being damaged by the voltage. However, when the current is too large, the current may damage the transistor. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A illustrates a schematic diagram of a cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure; FIG. 1B illustrates a schematic diagram of a cross-sectional view of a semiconductor structure according to another embodiment of the present disclosure; FIG. 1C illustrates a schematic diagram of a cross-sectional view of a semiconductor structure according to another embodiment of the present disclosure; FIG. 2A illustrates a schematic diagram of a cross-sectional view of a semiconductor structure according to another embodiment of the present disclosure; FIG. 2B illustrates a schematic diagram of a cross-sectional view of a semiconductor structure according to another embodiment of the present disclosure; FIG. 2C illustrates a schematic diagram of a cross-sectional view of a semiconductor structure according to another embodiment of the present disclosure; FIG. 3 illustrates a schematic diagram of a cross-sectional view of a semiconductor structure according to another embodiment of the present disclosure; FIGS. 4A to 4H illustrate schematic diagrams of manufacturing processes of the semiconductor structure in FIG. 1A; FIGS. 5A to 5J illustrate schematic diagrams of manufacturing processes of the semiconductor structure in FIG. 1B; FIGS. 6A to 6I illustrate schematic diagrams of manufacturing processes of the semiconductor structure in FIG. 2A; FIGS. 7A to 7K illustrate schematic diagrams of manufacturing processes of the semiconductor structure in FIG. 2B; and FIGS. 8A to 8I illustrate schematic diagrams of manufacturing processes of the semiconductor structure in FIG. 3. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Referring to FIG. 1A, FIG. 1A illustrates a schematic diagram of a cross-sectional view of a semiconductor structure 100 according to an embodiment of the present disclosure. The semiconductor structure 100 may be applied to a LDMOS (Laterally Diffused Metal Oxide Semiconductor) of a PMIC (Power Management IC), for example. As illustrated in FIG. 1A, the semiconductor structure 100 includes a substrate 110, a contact field plate 120, a transistor 130, at least on dielectric layer 140, at least on conductive via 150 and at least one conductive layer 160. The contact field plate 120 is disposed on the substrate 110 and includes an insulation layer 121, a poly gate 122, a first-type semiconductor doping region 123 and a second-type semiconductor doping region 124. The insulation layer 121 is disposed on the substrate 110, and the poly gate 122 is disposed over the insulation layer 121. The first-type semiconductor doping region 123 and the second-type semiconductor doping region 124 are disposed in the po