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US-20260129949-A1 - Package of GaN/SiC Cascode Power Device

US20260129949A1US 20260129949 A1US20260129949 A1US 20260129949A1US-20260129949-A1

Abstract

A GaN/SiC cascode power device is formed with first and second transistor groups. The first transistor group has one or more low-voltage normally-off GaN high-electron-mobility transistors. The second group has one or more high-voltage normally-on SiC junction-field-effect transistors. A backbone layer mechanically supports respective transistors in the two transistor groups and provides electrical connectivity among the respective transistors. The backbone layer is formed by embedding a network of conductive traces on or within an insulating rigid layer. The respective transistors are mounted on the backbone layer and electrically connected via the network of conductive traces. Advantageously, bonding wires are absent in providing intra-connection between the two transistor groups. Undesirable interconnection inductances are considerably reduced such that switching loss and switching oscillation, both overstressing the power device during a switching process, are suppressed.

Inventors

  • Jing Chen
  • Ji SHU

Assignees

  • THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Dates

Publication Date
20260507
Application Date
20250819

Claims (15)

  1. 1 . A GaN/SiC cascode power device comprising: a first transistor group consisting of one or more low-voltage (LV) normally-off GaN high-electron-mobility transistors (HEMTs); a second transistor group consisting of one or more high-voltage (HV) normally-on SiC junction field effect transistors (JFETs); and a backbone layer for mechanically supporting respective transistors in the first and second transistor groups and providing electrical connectivity among the respective transistors, wherein the backbone layer is formed by embedding a network of conductive traces on or within an insulating rigid layer, the respective transistors being mounted on the backbone layer and being electrically connected to the network of conductive traces.
  2. 2 . The GaN/SiC cascode power device of claim 1 , wherein: the first transistor group is arranged face-to-face with the second transistor group such that the first and second transistor groups are located on two mutually-opposite sides of the backbone layer; and the insulating rigid layer includes one or more through holes such that at least one conductive trace in the network of conductive traces runs through the one or more through holes for electrically connecting the first and second transistor groups.
  3. 3 . The GaN/SiC cascode power device of claim 1 , wherein the first transistor group is arranged side-by-side with the second transistor group such that the first and second transistor groups are located on a same side of the backbone layer.
  4. 4 . The GaN/SiC cascode power device of claim 1 , wherein: the second transistor group is further limited to consist of plural HV normally-on SiC JFETs; and the network of conductive traces is configured to electrically connect the plural HV normally-on SiC JFETs in parallel for boosting a current capacity handleable by the GaN/SiC cascode power device.
  5. 5 . The GaN/SiC cascode power device of claim 1 , wherein: the first transistor group is further limited to consist of plural LV normally-off GaN HEMTs; and the network of conductive traces is configured to electrically connect the plural LV normally-off GaN HEMTs in parallel for boosting a current capacity handleable by the GaN/SiC cascode power device.
  6. 6 . The GaN/SiC cascode power device of claim 1 , wherein: the first transistor group is further limited to consist of plural LV normally-off GaN HEMTs; the second transistor group is further limited to consist of plural HV normally-on SiC JFETs; and the network of conductive traces is configured to electrically connect the plural LV normally-off GaN HEMTs in parallel and to electrically connect the plural HV normally-on SiC JFETs in parallel for boosting a current capacity handleable by the GaN/SiC cascode power device.
  7. 7 . The GaN/SiC cascode power device of claim 1 , wherein: the first transistor group is further limited to consist of a single LV normally-off GaN HEMT; and the second transistor group is further limited to consist of a single HV normally-on SiC JFET.
  8. 8 . The GaN/SiC cascode power device of claim 1 further comprising one or more peripheral blocks, wherein each of the one or more peripheral blocks consists of one or more electronic components electrically connected to the first transistor group via the network of conductive traces.
  9. 9 . The GaN/SiC cascode power device of claim 8 , wherein the one or more peripheral blocks are integrated with the first transistor group.
  10. 10 . The GaN/SiC cascode power device of claim 8 , wherein each of the one or more electronic components is a gate driver, a controller, or a passive electronic component.
  11. 11 . The GaN/SiC cascode power device of claim 1 , wherein the backbone layer is realized as a direct bonding copper (DBC) layer, an active metal brazing (AMB) layer, a direct plating copper (DPC) layer, or an interposer layer.
  12. 12 . The GaN/SiC cascode power device of claim 1 , wherein the insulating rigid layer is composed of AlN, Al 2 O 3 , Si 3 N 4 , epoxy, polymer, or another insulating material.
  13. 13 . A power module comprising a plurality of power devices, wherein: each of respective power devices in the plurality of power devices is formed as the GaN/SiC cascode power device of claim 1 ; and respective insulating rigid layers of the respective power devices are planarly joined to form a single insulating sheet.
  14. 14 . The power module of claim 13 , wherein the single insulating sheet is composed of AlN, Al 2 O 3 , Si 3 N 4 , epoxy, polymer, or another insulating material.
  15. 15 . A GaN/SiC cascode power device comprising: a low-voltage (LV) normally-off GaN high-electron-mobility transistor (HEMT); and a high-voltage (HV) normally-on SiC junction field effect transistor (JFET); wherein a first pad pattern of the LV normally-off GaN HEMT matches a second pad pattern of the HV normally-on SiC JFET, and wherein the LV normally-off GaN HEMT is directly attached to the HV normally-on SiC JFET with the first and second pad patterns aligned to form the GaN/SiC cascode power device.

Description

ABBREVIATIONS Al2O3 aluminaAlN aluminum nitrideAMB active metal brazingDBC direct bonding copperDPC direct plating copper GaN gallium nitride HEMT high-electron-mobility transistorHV high-voltageJFET junction field-effect transistorLV low-voltageMOS metal-oxide-semiconductorMOSFET metal-oxide-semiconductor field-effect transistorPCB printed circuit boardSi3N4 silicon nitrideSiC silicon carbide TECHNICAL FIELD The present disclosure generally relates to a GaN/SiC cascode power device. Particularly, the present disclosure relates to packaging the GaN/SiC cascode power device for minimizing parasitic inductances. BACKGROUND The GaN/SiC cascode device uses a HV normally-on SiC JFET to block a high voltage and a LV normally-off GaN HEMT to gate current has recently been proposed and demonstrated with superior switching and static performance over SiC MOSFETs. Compared with the best commercial SiC MOSFETs, the GaN/SiC cascode device replaces the trap-rich low-mobility SiC MOS channel with a high-quality high-mobility GaN 2D electron gas channel, introducing the benefits of faster switching speed and much lower conduction loss. To fully exploit the fast-switching potential of GaN/SiC power devices, parasitic inductances are required to be minimized to mitigate switching oscillations and to suppress switching losses. For the GaN/SiC cascode device, the parasitic interconnection inductances are the most important ones as the gate of the JFET can be overstressed by the switching oscillations induced by the parasitic interconnection inductances, thereby affecting the reliability of the cascode power device. See J. SHU, Z. ZHENG and K. J. CHEN, “Protecting SiC JFET from Gate Overstress in GaN/SiC Cascode Device without Compromising Switching Performance,” IEEE Transactions on Power Electronics, pp. 5567-5575, May 2024, doi: 10.1109/TPEL.2024.3354833, and J. Shu et al., “3D Co-packaging of GaN/SiC Cascode Device for High-Frequency Power Switching Operation,” in 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Jun. 2024, pp. 486-489. doi: 10.1109/ISPSD59661.2024.10579564, the disclosures of both of which are incorporated by reference herein. U.S. Pat. No. 9,960,153 discloses a power device formed by connecting a JFET and a MOSFET in a cascode-coupling manner, where the JFET is formed by having two component JFETs connected in parallel. In packaging the power device, the two component JFETs and MOSFET are physically connected by bonding wires, which introduce considerable amounts of inductance. The GaN/SiC cascode power device demonstrated much faster switching speed than all commercial power devices, requiring minimized parasitic inductances. In addition, different from the conventional vertical silicon MOSFET, the GaN HEMT is planar in nature, potentially enabling new package solutions that never exist before. Therefore, there is an urgent need in the art for a new technique of packaging a GaN/SiC cascode power device with an aim of reducing inductances. SUMMARY A first aspect of the present disclosure is to provide a GaN/SiC cascode power device. The GaN/SiC cascode power device comprises a first transistor group, a second transistor group and a backbone layer. The first transistor group consists of one or more LV normally-off GaN HEMTs. The second transistor group consists of one or more HV normally-on SiC JFETs. The backbone layer is used for mechanically supporting respective transistors in the first and second transistor groups and providing electrical connection among the respective transistors. Particularly, the backbone layer is formed by forming a network of conductive traces on or within an insulating rigid layer. The respective transistors are mounted on the backbone layer and are electrically connected to the network of conductive traces. In certain embodiments, the first transistor group is arranged face-to-face with the second transistor group such that the first and second transistor groups are located on two mutually-opposite sides of the backbone layer. The insulating rigid layer includes one or more through holes such that at least one conductive trace in the network of conductive traces runs through the one or more through holes for electrically connecting the first and second transistor groups. In certain embodiments, the first transistor group is arranged side-by-side with the second transistor group such that the first and second transistor groups are located on a same side of the backbone layer. In certain embodiments, the second transistor group is further limited to consist of plural HV normally-on SiC JFETs. The network of conductive traces is configured to electrically connect the plural HV normally-on SiC JFETs in parallel for boosting a current capacity handleable by the GaN/SiC cascode power device. In certain embodiments, the first transistor group is further limited to consist of plural LV normally-off GaN HEMTs. The network of conductive traces is configu