US-20260129950-A1 - SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME

Abstract

A semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes circuit elements on a first substrate, a lower interconnection structure coupled with the circuit elements, and a lower bonding structure coupled with the lower interconnection structure. The second semiconductor structure includes an upper bonding structure bonded to the lower bonding structure, a conductive layer, a stack structure including interlayer insulating layers and gate electrodes, a plurality of separation regions at least partially penetrating through the stack structure, channel structures including a channel layer and at least partially penetrating through the stack structure, a plurality of address studs spaced apart from each other by a first separation distance, a plurality of channel studs below the channel structures, and an upper interconnection structure below the stack structure, coupled with the plurality of channel studs, and spaced apart from the plurality of address studs.

Inventors

• Byunggon PARK
• Hyunsyek OH
• Junbeom PARK
• Yongjoon Shin
• Soosik OH
• Moongeun KIM

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20250428

Priority Date

20241107

Claims (20)

1. 1 . A semiconductor device, comprising: a first semiconductor structure comprising: a first substrate; circuit elements on the first substrate; a lower interconnection structure coupled with the circuit elements; and a lower bonding structure coupled with the lower interconnection structure; and a second semiconductor structure comprising: an upper bonding structure bonded to the lower bonding structure; a conductive layer; a stack structure comprising interlayer insulating layers and gate electrodes laminated in a first direction below the conductive layer, the first direction being perpendicular to an upper surface of the conductive layer; a plurality of separation regions at least partially penetrating through the stack structure, extending in a second direction, and spaced apart from each other in a third direction, the second direction being perpendicular to the first direction, the third direction being perpendicular to the first direction and the second direction; channel structures comprising a channel layer and at least partially penetrating through the stack structure in the first direction; a plurality of address studs spaced apart from each other by a first separation distance in the second direction below at least one separation region of the plurality of separation regions; a plurality of channel studs below the channel structures; and an upper interconnection structure below the stack structure, coupled with the plurality of channel studs, and spaced apart from the plurality of address studs.
2. 2 . The semiconductor device of claim 1 , wherein each address stud of the plurality of address studs comprises a first upper surface, a first lower surface, and a first side surface between the first upper surface and the first lower surface, wherein each channel stud of the plurality of channel studs comprises a second upper surface, a second lower surface, and a second side surface between the second upper surface and the second lower surface, and wherein first lower surfaces of the plurality of address studs are disposed on a same level as second lower surfaces of the plurality of channel studs.
3. 3 . The semiconductor device of claim 2 , wherein first upper surfaces of the plurality of address studs are disposed below third lower surfaces of the at least one separation region, wherein a width of the first upper surface of each address stud of the plurality of address studs is less than a width of the first lower surface of that address stud, and wherein widths of the third lower surfaces of the at least one separation region are greater than the width of the first lower surface of each address stud of the plurality of address studs.
4. 4 . The semiconductor device of claim 3 , wherein the third lower surfaces of the at least one separation region are spaced apart from the first upper surface of each address stud of the plurality of address studs in the first direction.
5. 5 . The semiconductor device of claim 3 , further comprising: a base layer between the third lower surfaces of the at least one separation region and the first upper surface of each address stud of the plurality of address studs.
6. 6 . The semiconductor device of claim 2 , wherein a first reference line passing through a center of the upper surface of each address stud of the plurality of address studs in the first direction is offset with respect to a second reference line passing through a center of a width of the at least one separation region in the third direction.
7. 7 . The semiconductor device of claim 2 , further comprising: an upper insulating layer between the first lower surface of each address stud of the plurality of address studs and the upper interconnection structure, wherein the plurality of address studs are isolated from the upper interconnection structure by the upper insulating layer.
8. 8 . The semiconductor device of claim 1 , wherein a first length of each address stud of the plurality of address studs in the first direction is equal to a second length of each channel stud of the plurality of channel studs in the first direction.
9. 9 . The semiconductor device of claim 1 , wherein a first length of each address stud of the plurality of address studs in the first direction is less than a second length of each channel stud of the plurality of channel studs in the first direction.
10. 10 . The semiconductor device of claim 1 , wherein the upper interconnection structure comprises bit lines coupled with the plurality of channel studs, extending in the third direction and spaced apart from each other in the second direction, and wherein the first separation distance is a multiple of a pitch of the bit lines.
11. 11 . The semiconductor device of claim 1 , further comprising: an upper gate electrode between the channel structures and the plurality of channel studs; upper channel structures at least partially penetrating through the upper gate electrode and coupled with each of the channel structures; and insulating regions at least partially penetrating through the upper gate electrode and disposed below the plurality of separation regions, wherein the plurality of address studs are disposed below the insulating regions.
12. 12 . The semiconductor device of claim 11 , wherein a first reference line passing through a center of upper surface of each address stud of the plurality of address studs in the first direction is coaxial with a second reference line passing through a center of a width of the at least one separation region in the third direction and is offset from a third reference line passing through a center of a width of each of the plurality of separation regions in the third direction.
13. 13 . The semiconductor device of claim 11 , wherein a width of the upper surface of each address stud of the plurality of address studs is less than a width of a lower surface of each separation region of the plurality of separation regions.
14. 14 . A semiconductor device, comprising: a first semiconductor structure comprising: a first substrate; circuit elements on the first substrate; a lower interconnection structure coupled with the circuit elements; and a lower bonding structure coupled with the lower interconnection structure; and a second semiconductor structure comprising: an upper bonding structure bonded to the lower bonding structure; a conductive layer; a stack structure comprising interlayer insulating layers and gate electrodes stacked in a first direction below the conductive layer, the first direction being perpendicular to an upper surface of the conductive layer; channel structures comprising a channel layer and at least partially penetrating through the stack structure in the first direction; a plurality of separation regions at least partially penetrating through the stack structure, extending in a second direction, and spaced apart from each other in a third direction, the second direction being perpendicular to the first direction, the third direction being perpendicular to the first direction and the second direction, the plurality of separation regions comprising address separation groups comprising first address separation regions and second address separation regions adjacent to the first address separation regions in the third direction; a plurality of address studs spaced apart from each other by multiples of a unit separation distance in the second direction, and disposed below the first address separation regions and the second address separation regions; and a plurality of channel studs disposed below the channel structures.
15. 15 . The semiconductor device of claim 14 , wherein the first address separation regions are disposed every n-th separation region of the plurality of separation regions in the third direction, n being a positive integer greater than zero (0), and wherein the second address separation regions comprise remaining separation regions of the plurality of separation regions except the first address separation regions.
16. 16 . The semiconductor device of claim 14 , wherein the plurality of address studs comprise at least one address stud disposed in a position determined based on a same array rule used to dispose each of the address separation groups.
17. 17 . The semiconductor device of claim 14 , wherein the plurality of address studs are disposed in different positions based on different array rules used to dispose the address separation groups.
18. 18 . The semiconductor device of claim 14 , further comprising: an upper interconnection structure coupled with the plurality of channel studs and spaced apart from the plurality of address studs, wherein the upper interconnection structure comprises bit lines coupled with the plurality of channel studs, extending in the third direction, and spaced apart from each other in the second direction, and wherein the unit separation distance is a multiple of a pitch of the bit lines.
19. 19 . A data storage system, comprising: a semiconductor storage device comprising: a first semiconductor structure comprising a substrate and circuit elements on the substrate; a second semiconductor structure comprising a stack structure comprising interlayer insulating layers and gate electrodes stacked in a first direction and channel structures at least partially penetrating through the stack structure; and an input/output pad coupled with the circuit elements; and a controller coupled with the semiconductor storage device via the input/output pad and configured to control the semiconductor storage device, wherein the first semiconductor structure further comprises: a lower interconnection structure coupled with the circuit elements; and a lower bonding structure coupled with the lower interconnection structure, wherein the second semiconductor structure further comprises: an upper interconnection structure disposed below the stack structure; an upper bonding structure coupled with the upper interconnection structure and bonded to the lower bonding structure; a plurality of separation regions at least partially penetrating through the stack structure and extending in a second direction, and spaced apart from each other in a third direction, the second direction being perpendicular to the first direction, the third direction being perpendicular to the first direction and the second direction; a plurality of address studs disposed below at least one separation region of the plurality of separation regions and spaced apart from each other by a first separation distance in the second direction; and a plurality of channel studs below the channel structures, and wherein the upper interconnection structure is coupled with the plurality of channel studs and spaced apart from the plurality of address studs.
20. 20 . The data storage system of claim 19 , wherein the plurality of address studs are disposed only below first address separation regions from among the plurality of separation regions, in the second direction, and wherein the first address separation regions are disposed every n-th separation region of the plurality of separation regions in the third direction, n being a positive integer greater than zero (0).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims benefit of priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0157340, filed on Nov. 7, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND 1. Field The present disclosure relates generally to semiconductor devices, and more particularly, to a semiconductor device and data storage systems including the same. 2. Description of Related Art Data storage systems, which may need data storage, may use a semiconductor device that may be capable of storing a relatively large amount of data. Accordingly, approaches for potentially increasing the data storage capacity of a semiconductor device may have been researched. For example, a possible approach for potentially increasing the data storage capacity of a semiconductor device may include three-dimensionally arranging memory cells of a semiconductor device, rather than arranging the memory cells two-dimensionally. SUMMARY One or more example embodiments of the present disclosure provide a semiconductor device having a relatively high reliability and capable of performing a quality inspection, when compared to a related semiconductor device. Accordingly, a highly reliable semiconductor device and a data storage system including the same may be provided through an error inspection having improved reliability. Further, one or more example embodiments of the present disclosure provide a data storage system including a semiconductor device having a relatively high reliability and capable of performing an error inspection operation. According to an aspect of the present disclosure, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate, circuit elements on the first substrate, a lower interconnection structure coupled with the circuit elements, and a lower bonding structure coupled with the lower interconnection structure. The second semiconductor structure includes an upper bonding structure bonded to the lower bonding structure, a conductive layer, a stack structure including interlayer insulating layers and gate electrodes laminated in a first direction below the conductive layer, a plurality of separation regions at least partially penetrating through the stack structure, extending in a second direction, and spaced apart from each other in a third direction, channel structures including a channel layer and at least partially penetrating through the stack structure in the first direction, a plurality of address studs spaced apart from each other by a first separation distance in the second direction below at least one separation region of the plurality of separation regions, a plurality of channel studs below the channel structures, and an upper interconnection structure below the stack structure, coupled with the plurality of channel studs, and spaced apart from the plurality of address studs. The first direction is perpendicular to an upper surface of the conductive layer. The second direction is perpendicular to the first direction. The third direction is perpendicular to the first direction and the second direction. According to an aspect of the present disclosure, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate, circuit elements on the first substrate, a lower interconnection structure coupled with the circuit elements, and a lower bonding structure coupled with the lower interconnection structure. The second semiconductor structure includes an upper bonding structure bonded to the lower bonding structure, a conductive layer, a stack structure including interlayer insulating layers and gate electrodes stacked in a first direction below the conductive layer, channel structures including a channel layer and at least partially penetrating through the stack structure in the first direction, a plurality of separation regions at least partially penetrating through the stack structure, extending in a second direction, and spaced apart from each other in a third direction, a plurality of address studs spaced apart from each other by multiples of a unit separation distance in the second direction, and disposed below the first address separation regions and the second address separation regions, and a plurality of channel studs disposed below the channel structures. The first direction is perpendicular to an upper surface of the conductive layer. The second direction is perpendicular to the first direction. The third direction is perpendicular to the first direction and the second direction. The plurality of separation regions include address separation groups including first address separation regions and second address separation regions adjacent to the first address separation region