US-20260129951-A1 - SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME

Abstract

An example semiconductor device includes a first semiconductor structure including a first semiconductor substrate and a first interconnection layer disposed on the first semiconductor substrate and including first interconnection structures and first bonding pads connected to the first interconnection structures and exposed on an upper surface; a second semiconductor structure including a second semiconductor substrate disposed on the first semiconductor structure, and a second interconnection layer disposed on the second semiconductor substrate, and including second interconnection structures, and second bonding pads connected to the second interconnection structures and exposed on a lower surface; and a buffer structure extending from at least one of side surfaces of the first semiconductor structure and the second semiconductor structure to a bonding surface between the first interconnection layer and the second interconnection layer.

Inventors

• Seongmin Son
• Joohee Jang
• Junhong MIN
• Seungdon Lee
• Hyunjin Lee
• Hojin Lee

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20250530

Priority Date

20241105

Claims (20)

1. 1 . A semiconductor chip, comprising: a first semiconductor structure including a first semiconductor substrate and a first interconnection layer, the first interconnection layer being disposed on the first semiconductor substrate and including a first plurality of interconnection structures and a first plurality of bonding pads, the first plurality of bonding pads being connected to the first plurality of interconnection structures and exposed on an upper surface of the first interconnection layer; a second semiconductor structure including a second semiconductor substrate and a second interconnection layer, the second semiconductor substrate being disposed on the first semiconductor structure, the second interconnection layer being disposed on the second semiconductor substrate and including a second plurality of interconnection structures and a second plurality of bonding pads, the second plurality of bonding pads being connected to the second plurality of interconnection structures and exposed on a lower surface of the second interconnection layer; and a buffer structure extending from at least one side surface of the first semiconductor structure and the second semiconductor structure to a bonding surface between the first interconnection layer and the second interconnection layer.
2. 2 . The semiconductor chip of claim 1 , wherein a first side surface of the first semiconductor structure and a second side surface of the second semiconductor structure are aligned in a vertical direction, and wherein the first side surface of the first semiconductor structure, the second side surface of the second semiconductor structure, and an external side surface of the buffer structure are coplanar with each other.
3. 3 . The semiconductor chip of claim 1 , wherein the buffer structure includes an insulating material.
4. 4 . The semiconductor chip of claim 1 , wherein the first plurality of bonding pads and the second plurality of bonding pads are bonded to each other and form a plurality of bonding structures, and the buffer structure extends from the at least one side surface of the first semiconductor structure and the second semiconductor structure toward an outermost bonding structure among the plurality of bonding structures.
5. 5 . The semiconductor chip of claim 4 , wherein an upper surface of the buffer structure contacts an upper surface of the first semiconductor structure, a lower surface of the buffer structure contacts a lower surface of the second semiconductor structure, and an internal side surface between the upper surface and the lower surface of the buffer structure contacts the outermost bonding structure.
6. 6 . The semiconductor chip of claim 1 , wherein the buffer structure includes: a first buffer layer having an external side surface extending from an internal side surface and disposed on an inner side of the at least one side surface of the first semiconductor structure and the second semiconductor structure; and a second buffer layer having an internal side surface contacts the external side surface of the first buffer layer and an external side surface coplanar with the at least one side surface of the first semiconductor structure and the second semiconductor structure.
7. 7 . The semiconductor chip of claim 6 , wherein the first buffer layer has a first density, and the second buffer layer has a second density greater than the first density.
8. 8 . The semiconductor chip of claim 6 , wherein the first buffer layer and the second buffer layer include a same insulating material, the insulating material in the first buffer layer has a first density, and the insulating material in the second buffer layer has a second density different than the first density.
9. 9 . The semiconductor chip of claim 6 , wherein a width of the first buffer layer is greater than a width of the second buffer layer.
10. 10 . The semiconductor chip of claim 4 , wherein an inner side surface of the buffer structure defines a space of the outermost bonding structure.
11. 11 . The semiconductor chip of claim 4 , wherein the outermost bonding structure includes a plurality of bonding structures spaced apart from each other, and wherein the buffer structure includes a region extending into a spacing between the plurality of bonding structures.
12. 12 . The semiconductor chip of claim 1 , wherein the first interconnection layer includes a first insulating layer exposing the first plurality of bonding pads on an upper portion of the first interconnection layer, and the second interconnection layer includes a second insulating layer exposing the second plurality of bonding pads on a lower portion of the second interconnection layer, and wherein the first insulating layer and the second insulating layer are bonded to each other.
13. 13 . The semiconductor chip of claim 1 , wherein the buffer structure extends from at least two side surfaces of the semiconductor chip.
14. 14 . The semiconductor chip of claim 1 , wherein the first semiconductor structure includes a plurality of memory cells, and wherein the second semiconductor structure includes a plurality of peripheral circuit devices driving the plurality of memory cells.
15. 15 . A semiconductor chip, comprising: a first semiconductor structure including a first semiconductor substrate and a first interconnection layer, the first interconnection layer being disposed on the first semiconductor substrate and including a first interconnection structure; a second semiconductor structure including a second semiconductor substrate and a second interconnection layer, the second semiconductor substrate being disposed on the first semiconductor structure, the second interconnection layer being disposed on a lower portion of the second semiconductor substrate and including a second interconnection structure; a plurality of bonding structures in which a first plurality of bonding pads and a second plurality of bonding pads are bonded to each other vertically, the first plurality of bonding pads being connected to the first interconnection structure and having a plurality of upper surfaces exposed from the first interconnection layer, the second plurality of bonding pads being connected to the second interconnection structure and having a plurality of lower surfaces exposed from the second interconnection layer; and a buffer structure provided at a side recess portion recessed from an outer side toward an outermost bonding structure among the plurality of bonding structures between an upper surface of the first interconnection layer and a lower surface of the second interconnection layer.
16. 16 . The semiconductor chip of claim 15 , wherein the side recess portion includes a slit shape between the upper surface of the first interconnection layer and the lower surface of the second interconnection layer.
17. 17 . The semiconductor chip of claim 15 , wherein the buffer structure includes: a first buffer layer having an internal side surface contacting the outermost bonding structure and an external side surface, the external side surface extending from an inner side surface and disposed on an inner side of the first semiconductor structure and the second semiconductor structure; and a second buffer layer having an internal side surface contacting an external side surface of the first buffer layer and an external side surface coplanar with a side surface of the first semiconductor structure.
18. 18 . The semiconductor chip of claim 17 , wherein the first buffer layer and the second buffer layer include a same insulating material, the first buffer layer has a first density, and the second buffer layer has a second density greater than the first density.
19. 19 . A semiconductor package, comprising: a base structure including a plurality of lower connection pads disposed on a lower surface of the base structure and a plurality of upper connection pads disposed on an upper surface of the base structure, the plurality of upper connection pads being electrically connected to the plurality of lower connection pads; at least one bonding chip structure disposed on the base structure, the at least one bonding chip structure including two semiconductor chip structures bonded to each other and a plurality of connection pads on a lower surface of the at least one bonding chip structure; and a plurality of solder bumps attaching the plurality of upper connection pads to the plurality of connection pads, wherein the at least one bonding chip structure includes: a first semiconductor structure including a first semiconductor substrate and a first interconnection layer, the first interconnection layer being disposed on the first semiconductor substrate and including a first plurality of interconnection structures and a first plurality of bonding pads, the first plurality of bonding pads being connected to the first plurality of interconnection structures and exposed on an upper surface of the base structure; a second semiconductor structure including a second semiconductor substrate and a second interconnection layer, the second semiconductor substrate being disposed on the first semiconductor structure, the second interconnection layer being disposed on a lower portion of the second semiconductor substrate and including a second plurality of interconnection structures and a second plurality of bonding pads, the second plurality of bonding pads being connected to the second plurality of interconnection structures and exposed on a lower surface of the base structure; and a buffer structure extending from at least one side surface of the first semiconductor structure and the second semiconductor structure to a bonding surface between the first interconnection layer and the second interconnection layer.
20. 20 . The semiconductor package of claim 19 , comprising: a sealant surrounding at least one bonding chip structure on the base structure.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims benefit of priority to Korean Patent Application No. 10-2024-0155058 filed on Nov. 5, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND As electronic devices have been designed to be lightweight and to have high-performance, a semiconductor chip having a reduced weight and high-performance is desired. High performance may be implemented by a stack structure of semiconductor chips, but a process of dicing and attaching a plurality of semiconductor chips formed on a semiconductor wafer may be performed individually, such that process yield may be lowered. SUMMARY The present disclosure relates to a bonded semiconductor device having improved reliability. In general, according to some aspects, a semiconductor device includes a first semiconductor structure including a first semiconductor substrate and a first interconnection layer disposed on the first semiconductor substrate and including first interconnection structures and first bonding pads connected to the first interconnection structures and exposed on an upper surface; a second semiconductor structure including a second semiconductor substrate disposed on the first semiconductor structure, and a second interconnection layer disposed on the second semiconductor substrate, and including second interconnection structures, and second bonding pads connected to the second interconnection structures and exposed on a lower surface; and a buffer structure extending from at least one of side surfaces of the first semiconductor structure and the second semiconductor structure to a bonding surface between the first interconnection layer and the second interconnection layer. In general, according to some aspects, a semiconductor device includes a first semiconductor structure including a first semiconductor substrate and a first interconnection layer disposed on the first semiconductor substrate and including a first interconnection structure; a second semiconductor structure including a second semiconductor substrate disposed on the first semiconductor structure, and a second interconnection layer disposed on a lower portion of the second semiconductor substrate and including a second interconnection structure; bonding structures in which first bonding pads connected to the first interconnection structure and having upper surfaces exposed from the first interconnection layer and second bonding pads connected to the second interconnection structure and having lower surfaces exposed from the second interconnection layer are bonded to each other vertically; and a buffer structure filling a side recess portion recessed from an outer side toward an outermost bonding structure among the bonding structures between an upper surface of the first interconnection layer and a lower surface of the second interconnection layer. In general, according to some aspects, a semiconductor device includes a base structure including lower connection pads disposed on a lower surface and upper connection pads disposed on an upper surface and electrically connected to the lower connection pads; at least one bonding chip structure disposed on the base structure, including two semiconductor chip structures bonded to each other, and including connection pads on a lower surface; and solder bumps attaching the upper connection pads to the connection pads, wherein the at least one bonding chip structure includes a first semiconductor structure including a first semiconductor substrate and a first interconnection layer disposed on the first semiconductor substrate and including first interconnection structures and first bonding pads connected to the first interconnection structures and exposed on an upper surface, on the base structure; a second semiconductor structure including a second semiconductor substrate disposed on the first semiconductor structure, and a second interconnection layer disposed on a lower portion of the second semiconductor substrate and including second interconnection structures and second bonding pads connected to the second interconnection structures and exposed on a lower surface; and a buffer structure extending from at least one side surface of the first semiconductor structure and the second semiconductor structure to a bonding surface between the first interconnection layer and the second interconnection layer. In general, according to some aspects, a method of manufacturing a semiconductor device includes disposing a first semiconductor wafer having a first thickness and including a first semiconductor substrate and a first interconnection layer on a carrier substrate; forming a bonded structure by attaching a second semiconductor wafer having a second thickness on the first semiconductor wafer; injecting a first filler into a first recess portion formed on an edge of a bonding surface between the first semiconductor