US-20260129953-A1 - INTERCONNECT STRUCTURE FOR FIN-LIKE FIELD EFFECT TRANSISTOR

Abstract

Interconnect structures and corresponding formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary interconnect structure for a FinFET includes a gate node via electrically coupled to a gate of the FinFET, a source node via electrically coupled to a source of the FinFET, and a drain node via electrically coupled to a drain of the FinFET. A source node via dimension ratio defines a longest dimension of the source node via relative to a shortest dimension of the source node via, and a drain node via dimension ratio defines a longest dimension of the drain node via relative to a shortest dimension of the drain node via. The source node via dimension ratio is greater than the drain node via dimension ratio. In some implementations, the source node via dimension ratio is greater than 2, and the drain node via dimension ratio is less than 1.2.

Inventors

• Jhon Jhy Liaw

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date

20260507

Application Date

20251219

Claims (20)

1. 1 . A device structure, comprising: a substrate; an active region over the substrate and extending lengthwise along a first direction; an isolation feature disposed over the substrate and interfacing a lower portion of the active region; a gate structure disposed over a channel region of the active region and extending lengthwise along a second direction perpendicular to the first direction; a source contact disposed over a source region of the active region; a drain contact disposed over a drain region of the active region; a source via landing on the source contact; and a drain via landing on the drain contact, wherein, along the second direction, a width of the source via is greater than a width of the drain via.
2. 2 . The device structure of claim 1 , wherein, in a top view, a shape of the source via is different from a shape of the drain via.
3. 3 . The device structure of claim 1 , wherein, in a top view, the source via comprises an elongated rectangular shape and the drain via comprises a circular shape.
4. 4 . The device structure of claim 1 , wherein the source contact comprises a first contact width along the second direction and a first contact length along the first direction, wherein the drain contact comprises a second contact width along the second direction and a second contact length along the first direction, wherein the first contact width is greater than the second contact width, wherein the first contact length is greater than the second contact length.
5. 5 . The device structure of claim 1 , wherein the active region comprises a pair of fins.
6. 6 . The device structure of claim 1 , further comprising: a silicide layer disposed between the source contact and the source region of the active region.
7. 7 . The device structure of claim 6 , wherein the silicide layer comprises nickel silicide, titanium silicide, or cobalt silicide.
8. 8 . The device structure of claim 1 , wherein the source contact and the drain contact comprise cobalt.
9. 9 . The device structure of claim 1 , wherein the source via and the drain via comprise tungsten or cobalt.
10. 10 . A device structure, comprising: a substrate; an active region over the substrate and extending lengthwise along a first direction; an isolation feature disposed over the substrate and interfacing a lower portion of the active region; a gate structure disposed over a channel region of the active region and extending lengthwise along a second direction perpendicular to the first direction; a source contact disposed over a source region of the active region; a drain contact disposed over a drain region of the active region; a dielectric layer disposed over the source contact and the drain contact; a source via extending through the dielectric layer to interface the source contact; and a drain via through the dielectric layer to interface the drain contact, wherein, along the second direction, a width of the source via is greater than a width of the drain via.
11. 11 . The device structure of claim 10 , wherein the source via and the drain via comprise tungsten or cobalt.
12. 12 . The device structure of claim 10 , wherein a sidewall of the source via are spaced apart from the dielectric layer by a first via barrier layer, wherein a sidewall of the drain via are spaced apart from the dielectric layer by a second via barrier layer, wherein the first via barrier layer and the second via barrier layer comprises titanium and nitrogen.
13. 13 . The device structure of claim 10 , wherein, in a top view, the source via comprises an elongated rectangular shape and the drain via comprises a circular shape.
14. 14 . The device structure of claim 10 , wherein the source contact comprises a first contact width along the second direction and a first contact length along the first direction, wherein the drain contact comprises a second contact width along the second direction and a second contact length along the first direction, wherein the first contact width is greater than the second contact width, wherein the first contact length is greater than the second contact length.
15. 15 . The device structure of claim 14 , wherein the substrate comprises a doped well region, wherein the active region is disposed over the doped well region.
16. 16 . The device structure of claim 15 , wherein the first contact width is greater than a width of the source region along the first direction such that the source contact overhangs the source region.
17. 17 . A device structure, comprising: a substrate; an active region over the substrate and extending lengthwise along a first direction; an isolation feature disposed over the substrate and interfacing a lower portion of the active region; a gate structure disposed over a channel region of the active region and extending lengthwise along a second direction perpendicular to the first direction; an epitaxial source feature over a source region of the active region; an epitaxial drain feature over a drain region of the active region; a source contact disposed over the epitaxial source feature; a drain contact disposed over the epitaxial drain feature; a source via landing on the source contact; and a drain via landing on the drain contact, wherein the source contact comprises a first contact width along the second direction and a first contact length along the first direction, wherein the drain contact comprises a second contact width along the second direction and a second contact length along the first direction, wherein the first contact width is greater than the second contact width, wherein the first contact length is greater than the second contact length, wherein, along the second direction, a width of the source via is greater than a width of the drain via.
18. 18 . The device structure of claim 17 , wherein the first contact width is between about 15 nm and about 400 nm.
19. 19 . The device structure of claim 17 , wherein the width of the source via is between about 15 nm and about 150 nm.
20. 20 . The device structure of claim 17 , wherein the source contact and the drain contact comprise cobalt.

Description

This is a continuation application of U.S. patent application Ser. No. 18/783,545, filed Jul. 25, 2024, which is continuation application of U.S. patent application Ser. No. 17/843,727, filed Jun. 17, 2022, which is a continuation application of U.S. patent application Ser. No. 17/120,563, filed Dec. 14, 2020, now U.S. Pat. No. 11,367,663, which is a continuation application of U.S. patent application Ser. No. 16/728,030, filed Dec. 27, 2019, now U.S. Pat. No. 10,867,871, which is a continuation application of U.S. patent application Ser. No. 15/691,452, filed Aug. 30, 2017, now U.S. Pat. No. 10,522,423, the entire disclosures of which are incorporated herein by reference. BACKGROUND The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, as fin-like field effect transistor (FinFET) technologies progress towards sub-micron feature sizes, decreasing fin pitches and increasing fin heights are placing significant constraints on multi-layer interconnect (MLI) features used to facilitate operation of FinFET devices. For example, interconnect structures currently provided in advanced technology node MLI features exhibit higher than desirable resistance and poor electromigration performance. Accordingly, although existing interconnect structures and corresponding formation techniques have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A is a simplified schematic top view of a fin-like field effect transistor (FinFET) device, in portion or entirety, having an interconnect structure that optimizes performance according to various aspects of the present disclosure. FIG. 1B is a diagrammatic cross-sectional view of the FinFET device of FIG. 1A along line B-B according to various aspects of the present disclosure. FIG. 1C is a diagrammatic cross-sectional view of the FinFET device of FIG. 1A along line C-C according to various aspects of the present disclosure. FIG. 1D is a diagrammatic cross-sectional view of the FinFET device of FIG. 1A along line D-D according to various aspects of the present disclosure. FIG. 2 is another diagrammatic cross-sectional view of the FinFET device of FIG. 1A along line D-D according to various aspects of the present disclosure. FIG. 3 is another simplified schematic top view of the FinFET device of FIGS. 1A-1D, in portion or entirety, according to various aspects of the present disclosure. FIG. 4 is yet another simplified schematic top view of the FinFET device of FIGS. 1A-1D, in portion or entirety, according to various aspects of the present disclosure. FIG. 5A is another diagrammatic cross-sectional view of the FinFET device of FIG. 1A along line B-B according to various aspects of the present disclosure. FIG. 5B is another diagrammatic cross-sectional view of the FinFET device of FIG. 1A along line C-C according to various aspects of the present disclosure. FIG. 6A is yet another diagrammatic cross-sectional view of the FinFET device of FIG. 1A along line B-B according to various aspects of the present disclosure. FIG. 6B is yet another diagrammatic cross-sectional view of the FinFET device of FIG. 1A along line C-C according to various aspects of the present disclosure. FIG. 7A is a simplified circuit diagram of a FinFET-based NAND logic circuit, in portion or entirety, according to various aspects of the present disclosure. FIG. 7B is a simplified schematic top view of an interconnect structure, in portion or entirety, of the FinFET-based NAND logic circuit of FIG. 7A according to various aspects of the present disclosure. FIG. 8A is a simplified circuit diagram of a FinFET-based NOR logic circuit, in portion or entirety, according to various aspects of the present disclosure. FIG. 8B is a simplified schematic top view