US-20260129954-A1 - SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

Abstract

A semiconductor structure is provided. The semiconductor structure includes a first protrusion over a substrate, a first plurality of nanostructures vertically stacked over the first protrusion, and a dielectric feature and an isolation structure over the substrate. The first protrusion is located between the dielectric feature and the isolation structure. The semiconductor structure further includes a plurality of spacer features interposed between the dielectric feature and the first plurality of nanostructures, and a gate dielectric layer wrapping around the first plurality of nanostructures. The gate dielectric layer extends along a top surface of the isolation structure.

Inventors

• BO-RONG LIN
• Kuo-Cheng Chiang
• SHI-NING JU
• Guan-Lin Chen
• Chih-Hao Wang

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20260105

Claims (20)

1. 1 . A semiconductor structure, comprising: a first protrusion over a substrate; a first plurality of nanostructures vertically stacked over the first protrusion; a dielectric feature and an isolation structure over the substrate, wherein the first protrusion is located between the dielectric feature and the isolation structure; a plurality of spacer features interposed between the dielectric feature and the first plurality of nanostructures; and a gate dielectric layer wrapping around the first plurality of nanostructures, wherein the gate dielectric layer extends along a top surface of the isolation structure.
2. 2 . The semiconductor structure as claimed in claim 1 , wherein the gate dielectric layer further extends along a top surface of the dielectric feature and surfaces of the plurality of spacer features.
3. 3 . The semiconductor structure as claimed in claim 1 , wherein the gate dielectric layer is interfaced with the plurality of spacer features and the dielectric feature.
4. 4 . The semiconductor structure as claimed in claim 1 , wherein one of the spacer features includes a first dielectric material and a second dielectric material between the first dielectric material and the dielectric feature, and the second dielectric material is different from the first dielectric material.
5. 5 . The semiconductor structure as claimed in claim 1 , wherein the gate dielectric layer includes a portion vertically between a first spacer feature and a second spacer feature in the plurality of spacer features.
6. 6 . The semiconductor structure as claimed in claim 1 , wherein the gate dielectric layer is interfaced with the dielectric feature.
7. 7 . The semiconductor structure as claimed in claim 1 , wherein the isolation structure includes a lower isolation layer and an upper isolation layer over the lower isolation layer, wherein a dielectric constant of the upper isolation layer is different from a dielectric constant of the lower isolation layer.
8. 8 . The semiconductor structure as claimed in claim 1 , wherein the top surface of the isolation structure is lower than a top surface of the first protrusion, and the top surface of the first protrusion is lower than a top surface of the dielectric feature.
9. 9 . The semiconductor structure as claimed in claim 1 , further comprising: a second protrusion over the substrate, wherein the dielectric feature is located between the first protrusion and the second protrusion; a second plurality of nanostructures vertically stacked over the second protrusion, wherein the gate dielectric layer wraps around the second plurality of nanostructures; a gate electrode layer over the gate dielectric layer, wherein the gate electrode layer continuously extends over the first protrusion, the dielectric feature and the second protrusion.
10. 10 . A semiconductor structure, comprising: a first protrusion and a second protrusion over a substrate; a first plurality of nanostructures over the first protrusion; a second plurality of nanostructures over the second protrusion; a dielectric feature between the first protrusion and the second protrusion; a first source/drain feature adjoining the first plurality of nanostructures; a second source/drain feature adjoining the second plurality of nanostructures; and an interlayer dielectric layer covering the first source/drain feature, the second source/drain feature and the dielectric feature, wherein the interlayer dielectric layer includes a portion embedded in the dielectric feature.
11. 11 . The semiconductor structure as claimed in claim 10 , further comprising: a gate stack wrapping around the first plurality of nanostructures and the second plurality of nanostructures, wherein the gate stack extends over the dielectric feature.
12. 12 . The semiconductor structure as claimed in claim 10 , wherein the portion of the interlayer dielectric layer embedded in the dielectric feature is located between the first source/drain feature and the second source/drain feature.
13. 13 . The semiconductor structure as claimed in claim 10 , further comprising: a first spacer feature between the dielectric feature and a first nanostructure in the first plurality of nanostructures; and a second spacer feature between the dielectric feature and a second nanostructure in the first plurality of nanostructures, wherein the first spacer feature is separated from the second spacer feature.
14. 14 . The semiconductor structure as claimed in claim 10 , further comprising: an isolation structure over the substrate, wherein the first protrusion is located between the isolation structure and the dielectric feature, wherein the isolation structure includes a first dielectric material and a second dielectric material above the first dielectric material, the second dielectric material is different from the first dielectric material, and the dielectric feature is made of the first dielectric material.
15. 15 . The semiconductor structure as claimed in claim 14 , wherein the first dielectric material and the second dielectric material of the isolation structure are interfaced with the first protrusion.
16. 16 . A method for forming a semiconductor structure, comprising: forming a first fin structure, a second fin structure and a third fin structure over a substrate; depositing a first dielectric material to fill a first trench between the first fin structure and the second fin structure and a second trench between the second fin structure and the third fin structure; etching the first dielectric material such that a first portion of the first dielectric material in the first trench is thinner than a second portion of the first dielectric material in the second trench; forming a second dielectric material on the first portion of the first dielectric material in the first trench, wherein a top surface of the second dielectric material is lower than a top surface of the second portion of the first dielectric material in the second trench; and forming a dummy gate structure over the first fin structure, the second fin structure and the third fin structure.
17. 17 . The method for forming the semiconductor structure as claimed in claim 16 , wherein a dielectric constant of the second dielectric material is lower than a dielectric constant of the first dielectric material.
18. 18 . The method for forming the semiconductor structure as claimed in claim 16 , further comprising: recessing the first fin structure, the second fin structure and the third fin structure to form a first recess, a second recess and a third recess, respectively; recessing the second portion of the first dielectric material in the second trench to form a fourth recess.
19. 19 . The method for forming the semiconductor structure as claimed in claim 18 , further comprising: forming a first source/drain feature, a second source/drain feature and a third source/drain feature in the first recess, the second recess and the third recess, respectively; and forming an interlayer dielectric layer to cover the first source/drain feature, the second source/drain feature and the third source/drain feature, wherein the fourth recess is filled by the interlayer dielectric layer.
20. 20 . The method for forming the semiconductor structure as claimed in claim 16 , further comprising, before depositing the first dielectric material: forming a third dielectric material in the first trench and the second trench; and removing a first portion of the third dielectric material in the first trench while leaving a second portion of the third dielectric material in the second trench.

Description

RELATED APPLICATIONS The present application is a continuation application of U.S. application Ser. No. 17/889,831, filed on Aug. 17, 2022 entitled of “SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME,” which is incorporated herein by reference in its entirety. BACKGROUND The electronics industry is experiencing an ever-increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). So far, these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such miniaturization has introduced greater complexity into the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology. Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the gate-all around transistor (GAA). The GAA device gets its name from the gate structure, which can extend around the channel region and provide access to the channel on two or four sides. GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their structure allows them to be aggressively scaled-down while maintaining gate control and mitigating SCEs. In conventional processes, GAA devices provide a channel in a silicon nanowire. However, integration of fabrication of the GAA features around the nanowire can be challenging. For example, while current methods have been satisfactory in many respects, continued improvements are still needed. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A, 1B, 1J, 1K, 1L, 1M, IN, 1O and 1P are perspective views illustrating the formation of a semiconductor structure at various intermediate stages, in accordance with some embodiments of the disclosure. FIGS. 1B-1, 1C, 1D, 1E, IF, 1G, 1H, 1I, 1J-2, 1J-3, 1J-4, 1L-1, 1L-2, 1L-3, 1O-1, 1O-2, 1O-3, 1Q, 1Q-1, 1Q-2, 1Q-3, 1R, 1S, 1S-1, 1S-2 and 1S-3 are cross-sectional views illustrating the formation of a semiconductor structure at various intermediate stages, in accordance with some embodiments of the disclosure. FIG. 1F-1 is an enlarge view of FIG. 1F to illustrate the deposition pores for forming the dielectric material, in accordance with some embodiments. FIG. 1J-1 is a plane view of the semiconductor structure of FIG. 1J, in accordance with some embodiments of the disclosure. FIG. 2 is a modification of the semiconductor structure of FIG. 1S, in accordance with some embodiments of the disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numerals are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method. The gate all around (GAA) transistor structures described below may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-p