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US-20260129955-A1 - ETCH STOP LAYER FOR REMOVAL OF SUBSTRATE IN STACKING TRANSISTORS AND METHODS OF FORMING THE SAME

US20260129955A1US 20260129955 A1US20260129955 A1US 20260129955A1US-20260129955-A1

Abstract

Embodiments utilize a silicon germanium layer deposited to a low germanium percentage under a substrate. The substrate is used to form a field effect transistor FET structure. After formation of the FET, the silicon germanium layer is oxidized to drive germanium to a concentrated sublayer of the silicon germanium layer. The sublayer is used as a stop layer to remove the oxidized portion of the silicon germanium layer.

Inventors

  • Yen Chuang
  • Ji-Yin Tsai
  • JET-RUNG CHANG
  • Zheng Hui Lim
  • Ta-Chun Ma

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date
20260507
Application Date
20260107

Claims (20)

  1. 1 . A method comprising: forming a silicon germanium layer over a substrate; forming first nanostructures over the silicon germanium layer, wherein the first nanostructures are vertically stacked; forming first source/drain regions on sidewalls of the first nanostructures; forming a first gate structure around the first nanostructures; oxidizing a first portion of the silicon germanium layer; and after oxidizing the first portion of the silicon germanium layer, using a second portion of the silicon germanium layer as a stop layer to remove the substrate and the first portion of the silicon germanium layer.
  2. 2 . The method of claim 1 , wherein oxidizing the first portion of the silicon germanium layer comprises oxidizing the first portion of the silicon germanium layer through the substrate.
  3. 3 . The method of claim 1 , wherein oxidizing the first portion of the silicon germanium layer comprises a thermal oxidation process or a plasma oxidation process.
  4. 4 . The method of claim 1 , wherein forming the silicon germanium layer comprises forming the silicon germanium layer to have a first germanium concentration, and wherein the second portion of the silicon germanium layer has a second germanium concentration after oxidizing the first portion of the silicon germanium layer, and wherein the second germanium concentration is greater than the first germanium concentration.
  5. 5 . The method of claim 4 , wherein the first germanium concentration is in a range of 5% to 20%.
  6. 6 . The method of claim 4 , wherein the second germanium concentration is in a range of 20% to 50%.
  7. 7 . The method of claim 1 , a ratio of a thickness of the silicon germanium layer prior to oxidizing the first portion of the silicon germanium layer to a thickness of the second portion of the silicon germanium layer is in a range of 2:1 to 10:1.
  8. 8 . The method of claim 1 further comprising: after removing the substrate and the first portion of the silicon germanium layer, removing the second portion of the silicon germanium layer; and forming an interconnect structure over a backside of the first nanostructures.
  9. 9 . The method of claim 8 , wherein removing the second portion of the silicon germanium layer comprises an etching process using a solution comprising HF and HNO as an etchant.
  10. 10 . The method of claim 1 , wherein a germanium concentration of the first portion of the silicon germanium layer is in a range of 0% and 10%.
  11. 11 . A method comprising: forming a silicon germanium layer over a substrate; forming a silicon layer over the silicon germanium layer; forming first nanostructures and second nanostructures over the silicon layer, wherein the first nanostructures and the second nanostructures are vertically stacked; forming a first gate structure surrounding the first nanostructures; forming a second gate structure over the first gate structure and surrounding the second nanostructures; performing a treatment process through the substrate to displace germanium from a first portion of the silicon germanium layer into a second portion of the silicon germanium layer; removing the substrate; using the second portion of the silicon germanium layer as an etch stop while removing the first portion of the silicon germanium layer; removing the second portion of the silicon germanium layer; and forming an interconnect structure over a backside of the silicon layer.
  12. 12 . The method of claim 11 , wherein the first nanostructures provide channel regions of a first nanostructure-FET, wherein a provide channel regions of a second nanostructure-FET, the first nanostructure-FET having a different conductivity type than the second nanostructure-FET.
  13. 13 . The method of claim 11 , wherein the treatment process comprises an oxidation process that oxidizes the substrate and the first portion of the silicon germanium layer.
  14. 14 . The method of claim 13 , wherein the oxidation process displaces germanium in the first portion of the silicon germanium layer with oxygen.
  15. 15 . The method of claim 11 , wherein the treatment process displaces 80% to 100% of the first portion of the silicon germanium layer into the second portion of the silicon germanium layer.
  16. 16 . The method of claim 11 , wherein a germanium concentration of the silicon germanium layer prior to the treatment process is in a range of 5% to 20%.
  17. 17 . A method comprising: forming a first interconnect structure over a device layer, the device layer comprising: a substrate; an etch stop layer over the substrate, the etch stop layer comprising an element at a first concentration; and a transistor over the etch stop layer; flipping the device layer over to expose a backside of the substrate; oxidizing the substrate and a first portion of the etch stop layer, wherein oxidizing the first portion of the etch stop layer increases a concentration the element in a second portion of the etch stop layer from the first concentration to a second concentration; and after oxidizing the substrate, removing the substrate and the etch stop layer; and forming a second interconnect structure over a remaining portion of the device layer.
  18. 18 . The method of claim 17 , wherein the element is germanium.
  19. 19 . The method of claim 17 , wherein the first concentration is in a range of 5% to 20%, and wherein the second concentration is in a range of 20% to 50%.
  20. 20 . The method of claim 19 , wherein a ratio of a total thickness of the etch stop layer to a thickness of the second portion of the etch stop layer is in a range of 2:1 to 10:1.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. application Ser. No. 18/365,763, filed on Aug. 4, 2023, which application is hereby incorporated herein by reference. BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates an example of a stacking transistor schematic in a three-dimensional view, in accordance with some embodiments. FIGS. 2-12 are views of intermediate stages in the manufacturing of stacking transistors, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. According to various embodiments, stacking transistors (e.g., complementary field effect transistors (CFETs)) are formed. A stacking transistor includes a lower nanostructure-FET and an upper nanostructure-FET. In some embodiments, the nanostructures may be formed over an etch stop layer (ESL) which is used to access the back side of the stacking transistor for forming a power rail and/or signals to the stacking transistor devices. Embodiments enhance the etch selectivity provided by the ESL while mitigating the risk of fracturing or cracking to occur in the ESL. The enhancement of the etch selectivity of the ESL is achieved by increasing the concentration of germanium by a condensing process that drives germanium from part of a silicon germanium layer to increase germanium percentage in another part of the silicon germanium layer. As a result, device performance and manufacturing ease of the completed stacking transistors can be improved. FIG. 1 illustrates an example of a stacking transistor (e.g., CFET) schematic, in accordance with some embodiments. FIG. 1 is a three-dimensional view, where some features of the stacking transistor are omitted for illustration clarity. The stacking transistors include multiple vertically stacked nanostructure-FETs (e.g., nanowire FETs, nanosheet FETs, multi bridge channel (MBC) FETs, nanoribbon FETs, gate-all-around (GAA) FETs, or the like). In other embodiments, the stacking transistors may include vertically stacked transistors of a different type than nanostructure-FETs (e.g., finFETs, or the like). For example, a stacking transistor may include a lower nanostructure-FET of a first device type (e.g., n-type/p-typ