US-20260129956-A1 - FIELD-EFFECT TRANSISTOR

US20260129956A1US 20260129956 A1US20260129956 A1US 20260129956A1US-20260129956-A1

Abstract

A recovery current is suppressed in a field-effect transistor having a deep layer. In the field-effect transistor, when a semiconductor substrate is viewed from above, contact layers are arranged at interval in a specific direction parallel to trenches in each inter-trench region. When the semiconductor substrate is viewed from above, deep layers are arranged at interval in the specific direction in each inter-trench region. In each inter-trench region, each interval between the contact layers is located above a corresponding one of the deep layers. In each inter-trench region, each interval between the deep layers is located below a corresponding one of the contact layers.

Inventors

Hidefumi Takaya

Assignees

DENSO CORPORATION

Dates

Publication Date: 20260507
Application Date: 20251218
Priority Date: 20230731

Claims (8)

1 . A field-effect transistor comprising: a semiconductor substrate made of a compound semiconductor and having a plurality of trenches formed on an upper surface of the semiconductor substrate; a plurality of gate electrodes respectively disposed in the plurality of trenches and insulated from the semiconductor substrate by a gate insulating film; and a source electrode in contact with the upper surface of the semiconductor substrate, wherein the semiconductor substrate has a plurality of n-type source layers, a plurality of p-type contact layers, a p-type body layer, an n-type drift layer, and a plurality of p-type deep layers, a semiconductor region located between the plurality of the trenches in the semiconductor substrate is an inter-trench region, the source layers are respectively disposed in the inter-trench regions, the source layer being in contact with the source electrode and being in contact with the gate insulating film, the contact layers are respectively disposed in the inter-trench regions and in contact with the source electrode, the plurality of contact layers are provided in each of the inter-trench regions, when the semiconductor substrate is viewed from above, the plurality of contact layers are arranged with an interval in a specific direction parallel to the plurality of trenches in each of the inter-trench regions, the body layer has a p-type impurity concentration lower than that of each of the contact layers, and is distributed across the plurality of inter-trench regions to be located below each of the source layers and each of the contact layers, and in contact with the gate insulating film, the drift layer is distributed across lower regions of the plurality of inter-trench regions to be in contact with the body layer from below in each of the inter-trench regions, and in contact with the gate insulating film, each of the deep layers extends from the body layer to a position lower than a lower end of each of the trenches, when the semiconductor substrate is viewed from above, the plurality of deep layers are arranged with an interval in the specific direction, in each of the inter-trench regions, each interval between the contact layers is located above the deep layer in each of the inter-trench regions, and each interval between the deep layers is located below the contact layer in each of the inter-trench regions.
2 . The field-effect transistor according to claim 1 , wherein each of the deep layers intersects each of the trenches when the semiconductor substrate is viewed from above.
3 . The field-effect transistor according to claim 1 , wherein each of the contact layers and each of the deep layers do not overlap each other when the semiconductor substrate is viewed from above.
4 . The field-effect transistor according to claim 1 , wherein in each of the inter-trench regions, the interval between the deep layer has a first part that overlaps with the contact layer when the semiconductor substrate is viewed from above, and a second part that does not overlap with the contact layer when the semiconductor substrate is viewed from above.
5 . The field-effect transistor according to claim 1 , wherein a lower end of each of the contact layers is located at the same position as or above a lower end of each of the source layers in a thickness direction of the semiconductor substrate.
6 . The field-effect transistor according to claim 1 , wherein each of the contact layers is positioned not in contact with the trench.
7 . The field-effect transistor according to claim 1 , wherein each of the source layers is positioned within an area adjacent to the trench and within the interval between the contact layers.
8 . The field-effect transistor according to claim 1 , wherein each of the source layers is positioned only within an area adjacent to the trench.

Description

CROSS REFERENCE TO RELATED APPLICATIONS The present application is a continuation application of International Patent Application No. PCT/JP2024/018533 filed on May 20, 2024, which designated the U.S. and claims the benefit of priority from Japanese Patent Application No. 2023-124922 filed on Jul. 31, 2023. The entire disclosures of all of the above applications are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a field-effect transistor. BACKGROUND A field-effect transistor has a trench-type gate electrode. The field-effect transistor has a p-type deep layer (called an electric field shield region on a lower side of base region) that extends downward from a p-type body layer (called a base region). SUMMARY According to an aspect of the present disclosure, a field-effect transistor includes: a semiconductor substrate made of a compound semiconductor and having trenches formed on an upper surface; gate electrodes respectively disposed in the trenches and insulated from the semiconductor substrate by a gate insulating film; and a source electrode in contact with the upper surface of the semiconductor substrate. The semiconductor substrate has plural n-type source layers, plural p-type contact layers, a p-type body layer, an n-type drift layer, and plural p-type deep layers. A semiconductor region of the semiconductor substrate located between the trenches is an inter-trench region. The source layers are respectively disposed in the inter-trench regions, and in contact with the source electrode and with the gate insulating film. The contact layers are respectively disposed in the inter-trench regions, and in contact with the source electrode. The contact layers are provided in each of the inter-trench regions. When the semiconductor substrate is viewed from above, in each of the inter-trench regions, the contact layers are arranged at a first interval in a specific direction parallel to the trenches. The body layer has a lower p-type impurity concentration than each of the contact layers, and is distributed across the inter-trench regions to be located below each of the source layers and each of the contact layers, in contact with the gate insulating film. The drift layer is distributed across the lower regions of the inter-trench regions, in contact with the body layer from below in each of the inter-trench regions, and in contact with the gate insulating film. Each of the deep layers extends from the body layer to a position lower than the lower end of each of the trenches. When the semiconductor substrate is viewed from above, the deep layers are arranged at a second interval in the specific direction, in each of the inter-trench regions. In each of the inter-trench regions, the first interval of the contact layers may be located above the deep layer. In each of the inter-trench regions, the second interval of the deep layers may be located below the contact layer. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a perspective view showing an xz cross-section and a yz cross-section of a switching element. FIG. 2 is an xz cross-sectional view of the switching element at a position not including a deep layer. FIG. 3 is an xz cross-sectional view of the switching element at a position including a deep layer. FIG. 4 is a yz cross-sectional view of the switching element at a position not including a trench. FIG. 5 is a plan view illustrating an upper surface of a semiconductor substrate. FIG. 6 is a graph showing impurity concentration distributions in a contact region, a body region, and a source region. FIG. 7 is a graph showing a drain current and a drain voltage during a recovery operation. FIG. 8 is a graph showing a relationship between a depth D and a surge voltage. FIG. 9 is a plan view of a switching element according to a first modification, corresponding to FIG. 5. FIG. 10 is a graph showing a relationship between a width W and a reduction rate of surge voltage. FIG. 11 is a plan view of a switching element according to a second modification, corresponding to FIG. 5. FIG. 12 is a plan view of a switching element according to a third modification, corresponding to FIG. 5. FIG. 13 is a plan view of a switching element according to a fourth modification, corresponding to FIG. 5. FIG. 14 is a plan view of a switching element according to a fifth modification, corresponding to FIG. 5. DETAILED DESCRIPTION A field-effect transistor has a trench-type gate electrode. The field-effect transistor has a p-type deep layer (called an electric field shield region on a lower side of base region) that extends downward from a p-type body layer (called a base region). The deep layer extends to a position below the lower end of the trench. A p-type contact layer that connects the body layer and the source electrode is provided above the deep layer. The contact layer is provided to stabilize the potential of the body layer. The deep layer is provided to reduce the electric field strength of th