US-20260129957-A1 - SILICON CARBIDE SEMICONDUCTOR DEVICE

US20260129957A1US 20260129957 A1US20260129957 A1US 20260129957A1US-20260129957-A1

Abstract

A silicon carbide semiconductor device, including: a semiconductor substrate having first and second main surfaces; a first semiconductor region and a second semiconductor region provided in the semiconductor substrate; third semiconductor regions selectively between the first main surface and the second semiconductor region; a plurality of gate electrodes provided in a plurality of trenches via a plurality of gate insulating films, respectively; second-conductivity-type regions selectively provided between the second semiconductor region and the first semiconductor region; first and second electrodes respectively provided on the first and second main surfaces; a fourth semiconductor region between the first main surface and the first semiconductor region; and a first wiring layer provided on the first main surface. The second-conductivity-type regions includes first second-conductivity-type regions apart from the trenches and in contact with the second semiconductor region. The first semiconductor region includes a first first-conductivity-type region having a different dopant concentration.

Inventors

Masakazu Baba

Assignees

FUJI ELECTRIC CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251229
Priority Date: 20240109

Claims (12)

1 . A silicon carbide semiconductor device comprising: a semiconductor substrate having an active region, the semiconductor substrate having a first main surface and a second main surface opposite to each other; a first semiconductor region of a first conductivity type, provided in the semiconductor substrate; a second semiconductor region of a second conductivity type, provided in the active region of the semiconductor substrate, between the first main surface and the first semiconductor region; a plurality of third semiconductor regions of the first conductivity type, selectively provided in the semiconductor substrate between the first main surface and the second semiconductor region; a plurality of trenches penetrating through the plurality of third semiconductor regions and the second semiconductor region in a depth direction of the silicon carbide semiconductor device; a gate insulating film provided in each of the plurality of trenches; a plurality of gate electrodes provided in the plurality of trenches via the gate insulating films, respectively; a plurality of second-conductivity-type regions selectively provided in the semiconductor substrate between the second semiconductor region and the first semiconductor region, reaching a position closer to the second main surface of the semiconductor substrate than are bottoms of the plurality of trenches, the plurality of second-conductivity-type regions being in contact with the first semiconductor region; a first electrode provided on the first main surface in the active region and electrically connected to the plurality of third semiconductor regions, the second semiconductor region and the plurality of second-conductivity-type regions; a second electrode provided on the second main surface; a fourth semiconductor region of the second conductivity type, provided in the semiconductor substrate between the first main surface and the first semiconductor region, and surrounding a periphery of the active region in a plan view of the silicon carbide semiconductor device, the fourth semiconductor region reaching a position closer to the second main surface than are the bottoms of the plurality of trenches and being in contact with the first semiconductor region; and a first wiring layer provided on the first main surface to surround the periphery of the active region, the first wiring layer being connected to a portion of the first electrode and being electrically connected to the fourth semiconductor region, the first wiring layer facing the fourth semiconductor region in the depth direction, wherein the plurality of second-conductivity-type regions includes a plurality of first second-conductivity-type regions provided apart from the plurality of trenches and in contact with the second semiconductor region, each of the plurality of first second-conductivity-type regions having a surface that faces the second main surface, and the first semiconductor region includes a first first-conductivity-type region having a dopant concentration different from that of the rest of the first semiconductor region, the first first-conductivity-type region being in contact with said surfaces of the plurality of first second-conductivity-type regions.
2 . The silicon carbide semiconductor device according to claim 1 , wherein the first semiconductor region further has a second first-conductivity-type region different from the first first-conductivity-type region, and the dopant concentration of the first first-conductivity-type region is higher than a dopant concentration of the second first-conductivity-type region.
3 . The silicon carbide semiconductor device according to claim 2 , wherein the first first-conductivity-type region is provided between the second semiconductor region and the second first-conductivity-type region, reaches a position closer to the second main surface than is the plurality of first second-conductivity-type regions, and selectively borders said surfaces of the plurality of first second-conductivity-type regions.
4 . The silicon carbide semiconductor device according to claim 2 , wherein the first semiconductor region further selectively includes a plurality of third first-conductivity-type regions between the second first-conductivity-type region and the plurality of first second-conductivity-type regions, the plurality of third first-conductivity-type regions being adjacent to the first first-conductivity-type region and having a dopant concentration lower than that of the second first-conductivity-type region.
5 . The silicon carbide semiconductor device according to claim 1 , wherein the first semiconductor region further has a second first-conductivity-type region different from the first first-conductivity-type region, and the dopant concentration of the first first-conductivity-type region is lower than a dopant concentration of the second first-conductivity-type region.
6 . The silicon carbide semiconductor device according to claim 5 , wherein the first first-conductivity-type region is provided between the second first-conductivity-type region and the plurality of first second-conductivity-type regions.
7 . The silicon carbide semiconductor device according to claim 2 , wherein the plurality of trenches extends linearly in a first direction parallel to the first main surface of the semiconductor substrate, the plurality of first second-conductivity-type regions is provided at a predetermined interval in the first direction, and the first first-conductivity-type region borders each of the plurality of first second-conductivity-type regions, reaches a position closer to the second main surface than is the plurality of first second-conductivity-type regions, and selectively borders said surfaces of the plurality of first second-conductivity-type regions.
8 . The silicon carbide semiconductor device according to claim 5 , wherein the plurality of trenches extends linearly in a first direction parallel to the first main surface of the semiconductor substrate, the plurality of first second-conductivity-type regions is provided at a predetermined interval in the first direction, and the first first-conductivity-type region has a plurality of portions each in an island-like shape, and each adjacent to a different one of the plurality of first second-conductivity-type regions in the depth direction.
9 . The silicon carbide semiconductor device according to claim 7 , wherein the predetermined interval is 1 μm or less.
10 . The silicon carbide semiconductor device according to claim 8 , wherein the predetermined interval is 1 μm or less.
11 . The silicon carbide semiconductor device according to claim 7 , wherein the plurality of second-conductivity-type regions includes a plurality of second second-conductivity-type regions facing the bottoms of the plurality of trenches, respectively, and extending linearly in the first direction.
12 . The silicon carbide semiconductor device according to claim 8 , wherein the plurality of second-conductivity-type regions includes a plurality of second second-conductivity-type regions facing the bottoms of the plurality of trenches, respectively, and extending linearly in the first direction.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This is a continuation application of International Application PCT/JP2024/042966 filed on Dec. 4, 2024 which claims priority from a Japanese Patent Application No. 2024-001297 filed on Jan. 9, 2024, the contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention Embodiments of the disclosure relate to a silicon carbide semiconductor device. 2. Description of the Related Art Japanese Patent No. 6617657 describes a technique in which a first p+ base region and a second p+ base region for electric field relaxation in the vicinity of a bottom of a trench are provided immediately below the trench (side facing an n+-type drain region) and between the trench and an adjacent, respectively, and a dopant concentration of an n-type current diffusion layer is made higher only immediately below the second p+ base region than in other portions, thereby making the breakdown voltage immediately below the first p+ base region higher than the breakdown voltage immediately below the second p+ base region. Japanese Laid-Open Patent Publication No. 2020-136416 also describes a similar technique. SUMMARY OF THE INVENTION According to an embodiment of the present disclosure, a silicon carbide semiconductor device includes: a semiconductor substrate having an active region, the semiconductor substrate having a first main surface and a second main surface opposite to each other; a first semiconductor region of a first conductivity type, provided in the semiconductor substrate; a second semiconductor region of a second conductivity type, provided in the active region of the semiconductor substrate, between the first main surface and the first semiconductor region; a plurality of third semiconductor regions of the first conductivity type, selectively provided in the semiconductor substrate between the first main surface and the second semiconductor region; a plurality of trenches penetrating through the plurality of third semiconductor regions and the second semiconductor region in a depth direction of the silicon carbide semiconductor device; a gate insulating film provided in each of the plurality of trenches; a plurality of gate electrodes provided in the plurality of trenches via the gate insulating films, respectively; a plurality of second-conductivity-type regions selectively provided in the semiconductor substrate between the second semiconductor region and the first semiconductor region, reaching a position closer to the second main surface of the semiconductor substrate than are bottoms of the plurality of trenches, the plurality of second-conductivity-type regions being in contact with the first semiconductor region; a first electrode provided on the first main surface in the active region and electrically connected to the plurality of third semiconductor regions, the second semiconductor region and the plurality of second-conductivity-type regions; a second electrode provided on the second main surface; a fourth semiconductor region of the second conductivity type, provided in the semiconductor substrate between the first main surface and the first semiconductor region, and surrounding a periphery of the active region in a plan view of the silicon carbide semiconductor device, the fourth semiconductor region reaching a position closer to the second main surface than are the bottoms of the plurality of trenches and being in contact with the first semiconductor region; and a first wiring layer provided on the first main surface to surround the periphery of the active region, the first wiring layer being connected to a portion of the first electrode and being electrically connected to the fourth semiconductor region, the first wiring layer facing the fourth semiconductor region in the depth direction. The plurality of second-conductivity-type regions includes a plurality of first second-conductivity-type regions provided apart from the plurality of trenches and in contact with the second semiconductor region, each of the plurality of first second-conductivity-type regions having a surface that faces the second main surface. The first semiconductor region includes a first first-conductivity-type region having a dopant concentration different from that of the rest of the first semiconductor region, the first first-conductivity-type region being in contact with said surfaces of the plurality of first second-conductivity-type regions. Objects, features, and advantages of the present invention are specifically set forth in or will become apparent from the following detailed description of the invention when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view depicting a layout of a silicon carbide semiconductor device according to an embodiment, as viewed from a front side of a semiconductor substrate thereof. FIG. 2 is a plan view depicting a layout of a cell structure of an active re