US-20260129958-A1 - SILICON CARBIDE MOSFET WITH INTEGRATED POLYSILICON-SILICON CARBIDE HETEROJUNCTION DIODE

US20260129958A1US 20260129958 A1US20260129958 A1US 20260129958A1US-20260129958-A1

Abstract

A semiconductor structure includes a semiconductor substrate of a first conductivity type. The semiconductor substrate can have an upper surface and a bottom surface. The semiconductor substrate can be made of polycrystalline silicon carbide. The semiconductor structure can further include a drift region of the first conductivity type located on the upper surface of the semiconductor substrate. The semiconductor structure can further include a first region of the upper surface of the semiconductor substrate including a formation region of a transistor, and a second region of the upper surface of the semiconductor substrate, adjacent to the first region, including a formation region of a Schottky barrier diode.

Inventors

Meng Chia LEE
Dilip Madhav Risbud

Assignees

RENESAS ELECTRONICS CORPORATION

Dates

Publication Date: 20260507
Application Date: 20241105

Claims (20)

1 . A semiconductor structure comprising: a semiconductor substrate of a first conductivity type having an upper surface and a bottom surface, the semiconductor substrate including polycrystalline silicon carbide; a drift region of the first conductivity type located on the upper surface of the semiconductor substrate; a first region of the upper surface of the semiconductor substrate including a formation region of a transistor; and a second region of the upper surface of the semiconductor substrate, adjacent to the first region, including a formation region of a Schottky barrier diode.
2 . The semiconductor structure of claim 1 , wherein the first region includes: a pair of channel regions of a second conductivity type opposite to the first conductivity type, the pair of channel regions located within the drift region; a pair of source regions of the first conductivity type disposed above and in contact with the pair of channel regions; and a gate electrode disposed above a first portion of an oxide layer, wherein the pair of source regions are adjacent to the gate electrode.
3 . The semiconductor structure of claim 2 , wherein the second region adjacent to the first region includes: a polysilicon layer within a trench on the drift region, the polysilicon layer providing a Schottky electrode; a second portion of the oxide layer disposed on opposing vertical sidewalls of the polysilicon layer, the second portion of the oxide layer having a gap located on a bottom surface of the polysilicon layer; and a second semiconductor region of a second conductivity type located within the drift region, wherein the gap in the second portion of the oxide layer allows the bottom surface of the polysilicon layer to contact the second semiconductor region for providing a polysilicon/SiC heterojunction diode.
4 . The semiconductor structure of claim 3 , wherein the Schottky electrode and the second semiconductor region are electrically connected at a bottom portion of the trench.
5 . The semiconductor structure of claim 4 , wherein the Schottky electrode and the second semiconductor region provide a Schottky barrier rectifier located at the bottom portion of the trench.
6 . The semiconductor structure of claim 3 , wherein the Schottky electrode and the pair of source regions are electrically connected to a source terminal.
7 . The semiconductor structure of claim 3 , wherein the Schottky electrode comprises a layer of the polycrystalline silicon carbide.
8 . The semiconductor structure of claim 4 , wherein a depth of the second semiconductor region within the drift region from the bottom portion of the trench varies between 0.1 um to 5 um.
9 . The semiconductor structure of claim 3 , wherein a dopant concentration of the second semiconductor region is more than 1×10 17 cm −3 and less than 1×10 20 cm −3 .
10 . The semiconductor structure of claim 3 , wherein the trench and the pair of source regions are separated by a predetermined distance varying between 0 um to 5 um.
11 . The semiconductor structure of claim 3 , further comprising: a first semiconductor region located between at least one source region of the pair of source regions and the trench; and a drain terminal disposed on a bottom surface of the semiconductor substrate.
12 . A semiconductor structure comprising: a drift region of a first conductivity type located on an upper surface of a semiconductor substrate of the first conductivity type, the drift region and the semiconductor substrate including polycrystalline silicon carbide; a JFET region of the first conductivity type disposed above the drift region, the JFET region including a vertical portion and a horizontal portion; a pair of channel regions disposed along the vertical portion and the horizontal portion of the JFET region; a pair of source regions adjacent to the JFET region, wherein each source region is abutted by a respective channel region and a first doped semiconductor region; and a Schottky electrode adjacent to the first doped semiconductor region, wherein an oxide layer electrically separates the Schottky electrode from the first doped semiconductor region, wherein the oxide layer covers vertical opposing sidewalls of the Schottky electrode and a gap located on a bottom portion of the oxide layer allows the Schottky electrode to contact a second doped semiconductor region located within the drift region.
13 . The semiconductor structure of claim 12 , wherein the Schottky electrode adjacent to the first doped semiconductor region comprises: a layer of polycrystalline silicon carbide substantially filling a trench within the drift region.
14 . The semiconductor structure of claim 13 , wherein the Schottky electrode being in contact with the second doped semiconductor region provides a Schottky barrier rectifier integrated within the semiconductor structure.
15 . The semiconductor structure of claim 12 , wherein the Schottky electrode and the pair of source regions are electrically connected to a source terminal.
16 . The semiconductor structure of claim 12 , further comprising: a drain terminal disposed on a bottom surface of the semiconductor substrate.
17 . A semiconductor structure comprising: a drift region of a first conductivity type located on an upper surface of a semiconductor substrate of the first conductivity type, the drift region and the semiconductor substrate including polycrystalline silicon carbide; a trench extending into the drift region; a polysilicon layer disposed within the trench; an oxide layer disposed on opposing vertical sidewalls of the polysilicon layer and between an upper part of the polysilicon layer and a lower part of the polysilicon layer, a bottom portion of the oxide layer including a gap; and a second doped semiconductor region within the drift region, wherein the gap on the bottom portion of the oxide layer allows the lower part of the polysilicon layer to contact the doped semiconductor region.
18 . The semiconductor structure of claim 17 , wherein the upper part of the polysilicon layer comprises a gate electrode and the lower part of the polysilicon layer comprises a Schottky electrode, wherein the oxide layer electrically separates the gate electrode from the Schottky electrode.
19 . The semiconductor structure of claim 18 , wherein the Schottky electrode being in contact with the doped semiconductor region provides a Schottky barrier rectifier integrated within the semiconductor structure.
20 . The semiconductor structure of claim 17 , further comprising: a first doped semiconductor region located between a pair of channel regions and above a base region, the base region disposed above a JFET region, wherein the trench is adjacent to at least one channel region of the pair of channel regions; a pair of source regions disposed above a respective channel region of the pair of channel regions; a source terminal disposed above the pair of source regions; and a drain terminal disposed on a bottom surface of the semiconductor substrate.

Description

BACKGROUND The present invention generally relates to the field of semiconductor devices, and more particularly to silicon carbide metal-oxide semiconductor field effect transistors. Despite having similar design elements, silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have a higher blocking voltage and higher thermal conductivity than silicon (Si) MOSFETs. SiC MOSFETs are used in medium-to high-voltage power systems since they can enable higher switching frequencies with improved efficiency while reducing the system size and the need for redundancy. SUMMARY According to an embodiment of the present disclosure, a semiconductor structure can include a semiconductor substrate of a first conductivity type. The semiconductor substrate can have an upper surface and a bottom surface. The semiconductor substrate can be formed by polycrystalline silicon carbide. The semiconductor structure can further include a drift region of the first conductivity type located on the upper surface of the semiconductor substrate. The semiconductor structure can further include a first region of the upper surface of the semiconductor substrate including a formation region of a transistor. The semiconductor structure can further include a second region of the upper surface of the semiconductor substrate, adjacent to the first region, including a formation region of a Schottky barrier diode. According to another embodiment of the present disclosure, a semiconductor structure can include a drift region of a first conductivity type located on an upper surface of a semiconductor substrate of the first conductivity type. The drift region and the semiconductor substrate can include polycrystalline silicon carbide. The semiconductor structure can further include a JFET region of the first conductivity type disposed above the drift region. The JFET region can include a vertical portion and a horizontal portion. The semiconductor structure can further include a pair of channel regions disposed along the vertical portion and the horizontal portion of the JFET region. The semiconductor structure can further include a pair of source regions adjacent to the JFET region. Each source region can be abutted by a respective channel region and a first doped semiconductor region. The semiconductor structure can further include a Schottky electrode adjacent to the first doped semiconductor region, wherein an oxide layer electrically separates the Schottky electrode from the first doped semiconductor region, wherein the oxide layer covers vertical opposing sidewalls of the Schottky electrode and a gap located on a bottom portion of the oxide layer allows the Schottky electrode to contact a second doped semiconductor region located within the drift region. According to yet another embodiment of the present disclosure, a semiconductor structure can include a drift region of a first conductivity type located on an upper surface of a semiconductor substrate of the first conductivity type. The drift region and the semiconductor substrate can include polycrystalline silicon carbide. The semiconductor structure can further include a trench extending into the drift region and a polysilicon layer disposed within the trench. The semiconductor structure can further include an oxide layer disposed on opposing vertical sidewalls of the polysilicon layer and between an upper part of the polysilicon layer and a lower part of the polysilicon layer. A bottom portion of the oxide layer can include a gap. The semiconductor structure can further include a doped semiconductor region within the drift region. The gap on the bottom portion of the oxide layer can allow the lower part of the polysilicon layer to contact the doped semiconductor region. BRIEF DESCRIPTION OF THE DRAWINGS The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, in which: FIG. 1 is a cross-sectional view of a semiconductor structure at an intermediate step during a semiconductor manufacturing process, according to an embodiment of the present disclosure; FIG. 2 is a cross-sectional view of the semiconductor structure after forming an oxide layer within a trench, according to an embodiment of the present disclosure; FIG. 3 is a cross-sectional view of the semiconductor structure after forming a nitride layer above the oxide layer, according to an embodiment of the present disclosure; FIG. 4 is a cross-sectional view of the semiconductor structure after forming a photoresist layer, according to an embodiment of the present disclosure; FIG. 5 is a cross-sectional view of the semiconductor structure after patterning the photoresist layer and etching the nitride layer, according to an embodiment of the present disclosure; FIG. 6 is a cross-sectional view of the semiconductor structure after removing a bottom portion of the oxide layer, accord