US-20260129960-A1 - BIASING ISOLATION REGION IN SEMICONDUCTOR SUBSTRATE

Abstract

In one example, an integrated circuit comprises: a first transistor coupled between a first power terminal and a second power terminal, the first transistor having a first control terminal; a resistor coupled between the first power terminal and the first control terminal; and a second transistor coupled between the first control terminal and a ground terminal, the second transistor having a second control terminal coupled to the first power terminal.

Inventors

• Orlando LAZARO
• John Russell Broze
• Timothy Bryan Merkin

Assignees

• TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date

20260507

Application Date

20251218

Claims (16)

1. 1 . An integrated circuit comprising: a first transistor coupled between a first power terminal and a second power terminal, the first transistor having a first control terminal; a resistor coupled between the first power terminal and the first control terminal; and a second transistor coupled between the first control terminal and a ground terminal, the second transistor having a second control terminal coupled to the first power terminal.
2. 2 . The integrated circuit of claim 1 , further comprising: a semiconductor substrate including an isolation region, the isolation region being an opposite conductivity type from the semiconductor substrate, the semiconductor substrate also including: a switch having a switch control terminal, and a driver circuit having a first power supply terminal and a driver output terminal, the switch control terminal coupled to the driver output terminal, and the first power supply terminal coupled to the second power terminal; and a bias circuit having a second power supply terminal and a bias terminal, the second power supply terminal coupled to the first power terminal, and the bias terminal coupled to the isolation region.
3. 3 . The integrated circuit of claim 2 , the isolation region includes at least one of: a buried layer, an n-well, or a p-well.
4. 4 . The integrated circuit of claim 2 , wherein the bias circuit includes: a rectifying device having a first positive terminal and a first negative terminal, the first positive terminal coupled to a current terminal of the switch, and the first negative terminal coupled to the bias terminal; a third transistor coupled between the bias terminal and the ground terminal, the third transistor having a third control terminal; and an amplifier having the second power supply terminal, a first amplifier input terminal, a second amplifier input terminal, and an amplifier output terminal, the first amplifier input terminal coupled to the bias terminal, the second amplifier input terminal coupled to the ground terminal, and the amplifier output terminal coupled to the third control terminal.
5. 5 . The integrated circuit of claim 4 , further comprising a fourth transistor coupled between the current terminal and the rectifying device.
6. 6 . The integrated circuit of claim 4 , further comprising a voltage offset circuit coupled between the bias terminal and the first amplifier input terminal.
7. 7 . The integrated circuit of claim 4 , wherein the amplifier has an offset between the first and second amplifier input terminals.
8. 8 . The integrated circuit of claim 4 , wherein the amplifier is a transconductance amplifier.
9. 9 . The integrated circuit of claim 8 , further comprising a capacitor coupled to the amplifier output terminal.
10. 10 . The integrated circuit of claim 4 , wherein the third transistor is an LDMOS transistor.
11. 11 . The integrated circuit of claim 4 , wherein the rectifying device includes at least one of: a diode, or a diode-connected transistor.
12. 12 . The integrated circuit of claim 2 , wherein the bias circuit is in the semiconductor substrate.
13. 13 . The integrated circuit of claim 2 , wherein the switch includes an LDMOS transistor.
14. 14 . The integrated circuit of claim 1 , wherein the first transistor is a p-type transistor.
15. 15 . The integrated circuit of claim 1 , wherein the second transistor is an LDMOS transistor.
16. 16 . The integrated circuit of claim 1 , wherein the first transistor and the resistor are configurable, responsive to a voltage at the first power terminal being below a threshold, disconnect the second power terminal from the first power terminal, and responsive to the voltage exceeding the threshold, connect the second power terminal to the first power terminal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional of U.S. Application No. 18/192,956 filed March 30, 2023, which claims priority to and the benefit of U.S. Provisional Patent Application Serial No. 63/330,601, filed on April 13, 2022, both of which are incorporated herein by reference in their entireties. BACKGROUND Charge may be injected into a semiconductor substrate of an integrated circuit during an operation of the circuit. The charge may be injected at regions within the semiconductor substrate. In some instances, the regions that receive the charge can have high-impedance, which may adversely affect the operation. SUMMARY This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided. Various disclosed devices and methods may be beneficially applied to a semiconductor substate that includes an isolation region and a P-N junction. While such embodiments may be expected to bias an isolation region in a manner that may reduce destructive snapback, no particular result is a requirement unless explicitly recited in a particular claim. An example described herein is an integrated circuit. The integrated circuit includes a semiconductor substrate, a first rectifying device, and a second rectifying device. The semiconductor substrate has a first region, a second region, and a third region each being an opposite conductivity type from the semiconductor substrate. The first region and the second region are respective current terminals of a transistor. The first rectifying device has a first positive terminal and a first negative terminal. The first positive terminal is coupled to the first region, and the first negative terminal is coupled to the third region. The second rectifying device has a second positive terminal and a second negative terminal. The second positive terminal is coupled to a ground terminal, and the second negative terminal is coupled to the third region. Another example is an integrated circuit. The integrated circuit includes a first transistor, a resistor, and a second transistor. The first transistor is coupled between a first power terminal and a second power terminal. The first transistor has a first control terminal. The resistor is coupled between the first power terminal and the first control terminal. The second transistor is coupled between the first control terminal and a ground terminal. The second transistor has a second control terminal coupled to the first power terminal. The foregoing summary outlines rather broadly various features of examples of the present disclosure in order that the following detailed description may be better understood. Additional features and advantages of such examples will be described hereinafter. The described examples may be readily utilized as a basis for modifying or designing other examples that are within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic illustrating a cross-sectional view of a portion of an integrated circuit according to some examples. FIG. 2 is a schematic illustrating an isolation region bias circuit and a switch device according to some examples. FIG. 3 is a schematic illustrating a cross-sectional view of a portion of an integrated circuit that includes an isolation region bias circuit and a switch device according to some examples. FIGS. 4A and 4B are schematics illustrating aspects of operations of the isolation region bias circuit and switch device of FIGS. 2 and 3 according to some examples. FIG. 5 is a schematic illustrating an isolation region bias circuit, a switch device, and a cascode device according to some examples. FIGS. 6A and 6B are schematics illustrating aspects of operations of the isolation region bias circuit, switch device, and cascode device of FIG. 5 according to some examples. FIG. 7 is a schematic of an isolation region bias circuit, a switch device, and a cascode device according to some examples. FIG. 8 is a schematic of an example operational transconductance amplifier (OTA) that can be part of the isolation region bias circuit of FIG. 7 according to some examples. FIG. 9 is a graph illustrating example current curves of a pull-up current, a pull-down current, and an output current the OTA of FIG. 8 according to some examples. FIG. 10 is a schematic of a system including the isolation region bias circuit, the switch device, and the cascode device of FIG. 7 according to some examples. The drawings, and accompanying detailed description, are provided for understanding of features of various examples and do not limit the scope of the appended claims. The examples illustrated in the drawings and described in the accompanying detailed description may be readily utilized as a basis for modifying or designing other examples that are within the scope of the appended claims. Identical reference numerals may be